參數(shù)資料
型號(hào)： M7040N-066ZA1T
廠商： 意法半導(dǎo)體
英文描述： CAP 0.01PF 50V 10% X7R AXIAL BULK P-MIL-PRF-39014
中文描述： 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎
文件頁(yè)數(shù)： 32/159頁(yè)
文件大小： 1088K
代理商： M7040N-066ZA1T
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M7040N
32/159
READ COMMAND
The READ can be a single read of a data array, a
mask array, an SRAM, or a register location
(CMD[2] = 0). It can be a burst READ (CMD[2] = 1)
or mask array locations using an internal auto-in-
crementing address register (RBURADR). Table
19, page 34 describes each type of READ com-
mand.
A single-location READ operation lasts six cycles,
as shown in Figure 18, page 33. The burst READ
adds two cycles for each successive READ. The
SADR[23:21] bits supplied in the READ Instruction
Cycle A drive SADR[23:21] signals during the
READ of an SRAM location.
The single READ operation takes six CLK cycles,
in the following sequence:
–
Cycle 1:
The host ASIC applies the READ In-
struction on the CMD[1:0] (CMD[2] = 0), using
CMDV = 1, and the DQ Bus supplies the ad-
dress, as shown in Table 20, page 34 and Table
21, page 35. The host ASIC selects the M7040N
for which ID[4:0] matches the DQ[25:21] lines. If
the DQ[25:21] = 11111, the host ASIC selects
the M7040N with the LDEV Bit set. The host
ASIC also supplies SADR[23:21] on CMD[8:6]
in Cycle A of the READ Instruction if the READ
is directed to the external SRAM.
–
Cycle 2:
The host ASIC floats DQ[71:0] to 3-
state condition.
–
Cycle 3:
The host ASIC keeps DQ[71:0] in 3-
state condition.
–
Cycle 4:
The selected device starts to drive the
DQ[71:0] Bus and drives the ACK signal from Z
to low.
–
Cycle 5:
The selected device drives the read
data from the addressed location on the
DQ[71:0] Bus and drives the ACK signal high.
–
Cycle 6:
The selected device floats DQ[71:0] to
3-state condition and drives the ACK signal low.
At the termination of Cycle 6, the selected device
releases the ACK line to 3-state condition. The
READ Instruction is complete, and a new opera-
tion can begin.
Note:
The latency of the SRAM READ will be dif-
ferent than the one described above (see SRAM
PIO Access, page 128). Table 20, page 34 lists
and describes the format of the READ address for
a data array, mask array, or SRAM.
In a burst READ operation, the READ lasts 4 + 2n
CLK-cycles (where
“
n
”
stands for the number of
accesses in the burst specified by the BLEN field
of the RBURREG). Table 21, page 35 describes
the READ address format for the internal registers.
Figure 19, page 33 illustrates the timing diagram
for the burst READ of the data or mask array. This
operation assumes that the host ASIC has pro-
grammed the RBURREG with the starting address
(ADR) and the length of transfer (BLEN) before ini-
tiating the burst READ command.
–
Cycle 1:
The host ASIC applies the READ In-
struction on the CMD[1:0] (CMD[2] = 1), using
CMDV=1 and the address supplied on the DQ
Bus, as shown in Table 22, page 35. The host
ASIC selects the M7040N for which ID[4:0]
matches the DQ[25:21] lines. If the DQ[25:21] =
11111, the host ASIC selects the M7040N with
the LDEV Bit set.
–
Cycle 2:
The host ASIC floats DQ[71:0] to the 3-
state condition.
–
Cycle 3:
The host ASIC keeps DQ[71:0] in the
3-state condition.
–
Cycle 4:
The selected device starts to drive the
DQ[71:0] Bus and drives ACK and EOT from Z
to low.
–
Cycle 5:
The selected device drives the READ
data from the addressed location on the
DQ[71:0] Bus and drives the ACK signal high.
Note:
Cycles four and five repeat for each addi-
tional access until all the accesses specified in
the burst length (BLEN) field of RBURREG are
complete. On the last transfer, the M7040N
drives the EOT signal high.
–
Cycle (4 + 2n):
The selected device drives the
DQ[71:0] to 3-state condition and drives the
ACK and the EOT signals low.
At the termination of Cycle 4 + 2n, the selected de-
vice floats the ACK line to 3-state condition. The
burst READ Instruction is complete, and a new op-
eration can begin (see Table 22, page 35 for burst
READ address formats).
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