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參數資料
| 型號： | M68Z128-55N1 |
| 廠商： | 意法半導體 |
| 英文描述： | 5V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
| 中文描述： | 5V的，1兆位的輸出128KB的x8低功耗SRAM啟用 |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 95K |
| 代理商： | M68Z128-55N1 |
1/12
March 2000
M68Z128
5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
I
ULTRA LOW DATA RETENTION CURRENT
– 10nA (typical)
– 2.0μA (max)
I
OPERATION VOLTAGE: 5V ±10%
I
128Kb x 8 VERY FAST SRAM with OUTPUT
ENABLE
I
EQUAL CYCLE and ACCESS TIMES: 55ns
I
LOW V
CC
DATA RETENTION: 2V
I
TRI-STATE COMMON I/O
I
LOW ACTIVE and STANDBY POWER
I
AUTOMATIC POWER-DOWN WHEN
DESELECTED
I
INTENDED FOR USE WITH ST
ZEROPOWER
AND TIMEKEEPER
CONTROLLERS
DESCRIPTION
The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
5V ±10% supply, and all inputs and outputs are
TTL compatible.
Figure 1. Logic Diagram
AI00647
17
A0-A16
W
DQ0-DQ7
VCC
M68Z128
G
E2
VSS
8
E1
TSOP32 (N)
8 x 20mm
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Input/Output
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M68Z128N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
| M68Z128W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
| M68Z128W-70N1 | 功能描述:RAM其它 4M (128Kx8) 70ns RoHS:否 制造商:Freescale Semiconductor 封裝:Tray |
| M68Z128W-70N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
| M68Z128WN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
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