參數(shù)資料
型號: M68HC711D3CFB1
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 87/124頁
文件大?。?/td> 5398K
代理商: M68HC711D3CFB1
PARALLEL I/O
TECHNICAL DATA
6-3
DDD[7:0] — Data Direction for Port D
When port D is a general-purpose I/O port, the DDRD register controls the direction of
the I/O pins as follows:
0 = Configures the corresponding port D pin for input
1 = Configures the corresponding port D pin for output
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W outputs.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as the slave
select (SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master
mode, DDD5 affects port D bit 5 as follows:
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK) to be
inputs, then they are inputs, regardless of the state of DDRD bits 2, 3, and 4. If the SPI
expects port D bits 2, 3, and 4 to be outputs, they are outputs only if DDRD bits 2, 3,
and 4 are set.
DDRA7 — Data Direction Control for Port A Bit 7
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
DDRA3 — Data Direction for Port A Bit 3
Overridden if an output compare function is configured to control the PA3 pin.
0 = Input only
1 = Output
PORTD — Port D Data
$0008
Bit 7
654321
Bit 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
RESET:
00000000
Alt. Func.:
R/W
AS
SCK
MOSI
MISO
TxD
RxD
DDRD — Data Direction Register for Port D
$0009
Bit 7
654321
Bit 0
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
RESET:
00000000
PACTL — Pulse Accumulator Control
$0026
Bit 7
654321
Bit 0
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
RESET:
00000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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