參數(shù)資料
型號: M68HC711D0CFN
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, PLCC-44
文件頁數(shù): 76/124頁
文件大?。?/td> 5398K
代理商: M68HC711D0CFN
RESETS AND INTERRUPTS
TECHNICAL DATA
5-11
The stacked return address can be used as a pointer to the illegal opcode so the illegal
opcode service routine can evaluate the offending opcode.
5.4.4 Software Interrupt
SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhib-
ited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit,
once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or
until user software clears the I bit in the CCR.
5.4.5 Maskable Interrupts
The maskable interrupt structure of the MCU can be extended to include additional ex-
ternal interrupt sources through the IRQ pin. The default configuration of this pin is a
low-level sensitive wired-OR network. When an event triggers an interrupt, a software
accessible interrupt flag is set. When enabled, this flag causes a constant request for
interrupt service. After the flag is cleared, the service request is released.
5.4.6 Reset and Interrupt Processing
Figure 5-1 and Figure 5-1 illustrate the reset and interrupt process. Figure 5-1 illus-
trates how the CPU begins from a reset and how interrupt detection relates to normal
opcode fetches. Figure 5-1 is an expansion of a block in Figure 5-1 and illustrates in-
terrupt priorities. Figure 5-2 shows the resolution of interrupt sources within the SCI
subsystem.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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