- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370993 > M68HC11CPU (Motorola, Inc.) Single-Chip Microcontrollers (AMCU) PDF資料下載
參數(shù)資料
| 型號： | M68HC11CPU |
| 廠商： | Motorola, Inc. |
| 英文描述： | Single-Chip Microcontrollers (AMCU) |
| 中文描述： | 單芯片微控制器（AMCU） |
| 文件頁數(shù)： | 12/31頁 |
| 文件大?。?/td> | 346K |
| 代理商： | M68HC11CPU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
Motorola Master Selection Guide
Single-Chip Microcontrollers (AMCU)
2.6–12
Modular Microcontrollers
Modular microcontrollers are another of the innovations
that make Motorola a leader in single–chip control systems.
Modular controllers are built up from standard modules that
interface via a common intermodule bus (IMB). The modular
concept allows rapid design and manufacture of controllers
tailored for specific applications.
Intermodule Bus Peripherals
Each modular microcontroller incorporates a state–of–the
art pipelined CPU module, a sophisticated integration module,
and
a
number
of
special–purpose
rapidly–growing library of special–purpose modules includes
programmable timers, serial communication interfaces,
analog–to–digital converters, and a variety of memory
modules.
Central Processing Units
CPU16
16–Bit Architecture
Full Set of 16–Bit Instructions
Three 16–Bit Index Registers
Two 16–Bit Accumulators
One Megabyte of Program Memory and One Megabyte
of Data Memory
Source code compatible with the M68HC11 CPU
Control–Oriented Digital Signal Processing Capability
High–Level Language Support
Fast Interrupt Response Time
Fully Static Implementation
Low Power Stop Operation
Background Debugging Mode
Hardware Breakpoint Signal
CPU32
32–Bit Internal Data Path and Arithmetic Hardware
32–Bit Internal Address Bus – 24–Bit External Address Bus
Eight 32–Bit General–Purpose Data Registers
Seven 32–Bit General–Purpose Address Registers
Separate User and Supervisor Stack Pointers and
Address Spaces
Separate Program and Data Address Spaces
Virtual Memory Implementation
Enhanced Addressing Modes
Object Code Compatible with M68000 Family
Improved Exception Handling for Controller Applications
Rich Instruction Set
Fully Static Implementation
Low Power Stop Operation
Background Debugging Mode
Hardware and Software Breakpoints
Trace on Change of Flow
Integration Modules
System Integration Module (SIM)
Manages controller internal and external bus interfaces
Provides device interrupt arbitration
Spurious interrupt monitor
modules.
The
Twelve programmable chip–select outputs
Watchdog timer, clock monitor, and bus monitor
PLL clock synthesizer
Single–Chip Integration Module (SCIM)
Manages controller internal and external bus interfaces
Provides device interrupt arbitration
Spurious interrupt monitor
Single–chip operation with address and data bus pins
configured as I/O ports
Optional Fully or Partially–expanded bus operation
Nine general–purpose chip select outputs
Emulation mode chip–select outputs can be used to
address a port replacement unit and external emulation
RAM
Watchdog timer, clock monitor, and bus monitor
PLL clock synthesizer
Interrupt request inputs can be configured for edge or
level detection
Reduced pin SCIM (RPSCIM) available with 5 chip selects
Timers
Time Processor Unit (TPU)
On–chip microengine dedicated to high–speed timing tasks
Two independent 16–bit counters used as basis for
timing tasks
Real–time task scheduler
Executes a programmed series of functions to perform
complex tasks
Each of 16 orthogonal channels can perform available
time functions
Functions contained in dedicated control store or in
MCU RAM
TPU communicates to CPU via dual port RAM
General Purpose Timer (GPT)
Two 16–bit free–running counters
Three input capture channels
Four output compare channels
One input capture/output compare channel
One pulse accumulator/event counter input
Two pulse–width modulation outputs
Pulse accumulator input
Configurable Timer Module (CTM)
Modular timer system combining different configurations
of timer submodules:
CPSM–6 TAP counter prescaler
FCSM–16–bit free running up counter
MCSM–16–bit modulus up counter
SASM–(Single Action) two I/O pins for 16–bit input
capture or output compare functions
DASM–(Dual Action) one I/O pin for 16–bit I/C, O/C,
PWM, or output function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68HC11 | Technical Data |
| M6M80011 | 1024 BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM |
| M6M80011AP | 1024 BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM |
| M6M80011FP | 1024 BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM |
| M6M80011L | 1024 BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M68HC11E | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| M68HC11E_03 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-channel, 8-bit analog-to-digital (A/D) converter |
| M68HC11E0 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:CONFIG Register Programming for EEPROM-based M68HC11 Microcontrollers |
| M68HC11E1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:CONFIG Register Programming for EEPROM-based M68HC11 Microcontrollers |
| M68HC11E8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:CONFIG Register Programming for EEPROM-based M68HC11 Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。