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參數(shù)資料
| 型號(hào)： | M68AW511AM70NC6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (512K x8) 3.0V Asynchronous SRAM |
| 中文描述： | 4兆位（為512k × 8）3.0V異步SRAM |
| 文件頁(yè)數(shù)： | 8/18頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | M68AW511AM70NC6T |
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M68AW511A
8/18
OPERATION
The M68AW511A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E = High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W and E as summarized in the Operat-
ing Modes table (Table 6).
Table 6. Operating Modes
Note: X = V
IH
or V
IL
.
Read Mode
The M68AW511A is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight of the 4,194,304
locations in the static memory array, specified by
the 19 address inputs. Valid data will be available
at the eight output pins within t
AVQV
after the last
stable address, providing G is Low and E is Low.
If Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
ELQV
or t
GLQV
) rather than the
address. Data out may be indeterminate at t
ELQX
and t
GLQX
, but data lines will always be valid at
t
AVQV
.
Figure 7. Address Controlled, Read Mode AC Waveforms
Note: E = Low, G = Low, W = High.
Operation
E
W
G
DQ0-DQ7
Power
Output Disabled
V
IL
X
V
IH
Hi-Z
Active (I
CC
)
Read
V
IL
V
IH
V
IL
Data Output
Active (I
CC
)
Write
V
IL
V
IL
X
Data Input
Active (I
CC
)
Deselect
V
IH
X
X
Hi-Z
Standby (I
SB
)
AI03034
tAVAV
tAVQV
tAXQX
A0-A18
DQ0-DQ7
VALID
DATA VALID
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| M68AW512DL55ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512K x16 3.0V Asynchronous SRAM |
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