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參數(shù)資料
| 型號(hào)： | M68AW256MN70ZB1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (256K x16) 3.0V Asynchronous SRAM |
| 中文描述： | 4兆位（256K × 16）3.0V異步SRAM |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 161K |
| 代理商： | M68AW256MN70ZB1T |
M68AW256M
12/20
Write Mode
The M68AW256M is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted
during
Address
subsequent write cycles. When E (W) is Low, and
UB or LB is Low, write cycle begins on the W (E)’s
falling edge. When E and W are Low, and UB = LB
= High, write cycle begins on the first falling edge
of UB or LB. Therefore, address setup time is
referenced to Write Enable, Chip Enable or UB/LB
as t
AVWL
, t
AVEL
and t
AVBL
respectively, and is
determined by the latter occurring edge.
transitions
for
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB.
If the Output is enabled (E = Low, G = Low, LB or
UB = Low), then W will return the outputs to high
impedance within t
WLQZ
of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for t
DVWH
before the rising edge of Write Enable, or for t
DVEH
before the rising edge of E, or for t
DVBH
before the
rising edge of UB/LB whichever occurs first, and
remain valid for t
WHDX
, t
EHDX
and t
BHDX
respec-
tively.
Figure 11. Write Enable Controlled, Write AC Waveforms
AI03958
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A17
E
W
DQ0-DQ15
VALID
tAVWH
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
tBLWH
UB, LB
tELWH
DATA
(1)
DATA
(1)
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| M68AW256MN70ZB6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (256K x16) 3.0V Asynchronous SRAM |
| M68AW256MN70ZB6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (256K x16) 3.0V Asynchronous SRAM |
| M68AW256MN70ZB6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (256K x16) 3.0V Asynchronous SRAM |
| M68AW256MN70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (256K x16) 3.0V Asynchronous SRAM |
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