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參數(shù)資料
| 型號： | M68AW256MN55ND1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (256K x16) 3.0V Asynchronous SRAM |
| 中文描述： | 4兆位（256K × 16）3.0V異步SRAM |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 161K |
| 代理商： | M68AW256MN55ND1T |
15/20
M68AW256M
Figure 14. Low V
CC
Data Retention AC Waveforms
Table 9. Low V
CC
Data Retention Characteristics
Symbol
Parameter
Note: 1. All other Inputs at V
IH
≥
V
CC
–0.2V or V
IL
≤
0.2V.
2. Tested initially and after any design or process changes that may affect these parameters. t
AVAV
is Read cycle time.
3. No input may exceed V
CC
+0.2V.
Test Condition
Min
Typ
Max
Unit
I
CCDR(1)
Supply Current (Data Retention)
V
CC
= 1.5V, E
≥
V
CC
–0.2V or
UB = LB
≥
V
CC
–0.2V, f = 0
(3)
4.5
9
μA
t
CDR(1,2)
Chip Deselected to Data
Retention Time
0
ns
t
R(2)
Operation Recovery Time
t
AVAV
ns
V
DR(1)
Supply Voltage (Data Retention)
E
≥
V
CC
–0.2V or
UB = LB
≥
V
CC
–0.2V, f = 0
1.5
V
AI03989
DATA RETENTION MODE
tR
3.6V
tCDR
VCC 2.7V
VDR> 1.5V
E
≥
VDR– 0.2V or UB=LB
≥
VDR– 0.2V
E, UB/LB
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