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參數(shù)資料
| 型號(hào)： | M68AW127BNK |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1Mbit 128K x8, 3.0V Asynchronous SRAM |
| 中文描述： | 1Mbit的128K的× 8，3.0V異步SRAM |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 327K |
| 代理商： | M68AW127BNK |
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M68AW127B
8/20
OPERATION
The M68AW127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 6).
Table 6. Operating Modes
Note: X = V
IH
or V
IL
.
Read Mode
The M68AW127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within t
AVQV
after the last stable address, provid-
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(t
ELQV
or t
GLQV
) rather than the address. Data out
may be indeterminate at t
ELQX
and t
GLQX
, but data
lines will always be valid at t
AVQV
.
Figure 8. Address Controlled, Read Mode AC Waveforms
Note: E1 = Low, E2 = High, G = Low, W = High.
Operation
E1
E2
W
G
DQ0-DQ7
Power
Read
V
IL
V
IH
V
IH
V
IH
Hi-Z
Active (I
CC
)
Read
V
IL
V
IH
V
IH
V
IL
Data Output
Active (I
CC
)
Write
V
IL
V
IH
V
IL
X
Data Input
Active (I
CC
)
Deselect
V
IH
X
X
X
Hi-Z
Standby (I
SB
)
Deselect
X
V
IL
X
X
Hi-Z
Standby (I
SB
)
AI05474
tAVAV
tAVQV
tAXQX
A0-A16
DQ0-DQ7
VALID
DATA VALID
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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