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參數(shù)資料
| 型號： | M68AW031A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CLAMP |
| 中文描述： | 256千位（32K的× 8）3.0V異步SRAM |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 147K |
| 代理商： | M68AW031A |
11/19
M68AW031A
Write Mode
The M68AW031A is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted
during
Address
subsequent write cycles. When E (W) is Low, write
cycle begins on the W (E)’s falling edge.
Therefore, address setup time is referenced to
Write Enable or Chip Enable as t
AVWL
and t
AVEL
respectively, and is determined by the latter
occurring edge.
transitions
for
The Write cycle can be terminated by the earlier
rising edge of E or W.
If the Output is enabled (E = Low, G = Low), then
W will return the outputs to high impedance within
t
WLQZ
of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for t
DVWH
before the rising
edge of Write Enable, or for t
DVEH
before the rising
edge of E, whichever occurs first, and remain valid
for t
WHDX
and t
EHDX
respectively.
Figure 12. Write Enable Controlled, Write AC Waveforms
Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied.
AI05941
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A14
E
W
DQ0-DQ7
VALID
tAVWH
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
tELWH
DATA
(1)
DATA
(1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68AW031AL70MS6U | CLAMP |
| M68AW031AL70N6U | CLAMP |
| M68AW031AL70NS6U | CLAMP |
| M68AW031AM70MS6U | CAC 5C 5#16S SKT PLUG |
| M68AW031AM70N6U | CAC 5C 5#16S SKT PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M68AW031AL70MS1U | 功能描述:RAM其它 256K (32Kx8) 70ns RoHS:否 制造商:Freescale Semiconductor 封裝:Tray |
| M68AW031AL70MS6U | 制造商:STMicroelectronics 功能描述: |
| M68AW031AL70N1 | 功能描述:RAM其它 256K (32Kx8) 70ns RoHS:否 制造商:Freescale Semiconductor 封裝:Tray |
| M68AW031AL70N1T | 制造商:STMicroelectronics 功能描述: |
| M68AW031AL70N6U | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit (32K x8) 3.0V Asynchronous SRAM |
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