參數(shù)資料
型號: M68AF511AM55NC6T
廠商: 意法半導體
英文描述: 4 Mbit (512K x8), 5V Asynchronous SRAM
中文描述: 4兆位(為512k × 8),5V的異步SRAM
文件頁數(shù): 11/18頁
文件大?。?/td> 129K
代理商: M68AF511AM55NC6T
11/18
M68AF511A
Write Mode
The M68AF511A is in the Write mode whenever
the W and E pins are Low. Either the Chip Enable
input (E) or the Write Enable input (W) must be de-
asserted during Address transitions for subse-
quent write cycles. Write begins with the concur-
rence of Chip Enable being active with W low.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as t
AVWL
and t
AVEH
respectively, and is determined by the latter occur-
ring edge.
The Write cycle can be terminated by the earlier
rising edge of E, or W.
if the Output is enabled (E = Low and G = Low),
then W will return the outputs to high impedance
within t
WLQZ
of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for t
DVWH
before the ris-
ing edge of Write Enable, or for t
DVEH
before the
rising edge of E, whichever occurs first, and re-
main valid for t
WHDX
or t
EHDX
.
Figure 10. Write Enable Controlled, Write AC Waveforms
Note: 1. During this period DQ0-DQ7 are in output state and input signal should not be applied.
AI05913
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A18
E
W
DQ0-DQ7
VALID
tAVWH
tELWH
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
DATA
(1)
DATA
(1)
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相關代理商/技術參數(shù)
參數(shù)描述
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