參數(shù)資料
型號(hào): M68AF031AM70NS1T
廠商: 意法半導(dǎo)體
英文描述: 256 Kbit (32K x 8) 5.0V Asynchronous SRAM
中文描述: 256千位(32K的× 8)5.0V異步SRAM
文件頁(yè)數(shù): 12/22頁(yè)
文件大?。?/td> 383K
代理商: M68AF031AM70NS1T
M68AF031A
12/22
Table 7. Read and Standby Mode AC Characteristics
Note: 1. Test conditions assume transition timing reference level = 0.3V
CC
or 0.7V
CC
.
2. At any given temperature and voltage condition, t
GHQZ
is less than t
GLQX
and t
EHQZ
is less than t
ELQX
for any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters.
Symbol
Parameter
M68AF031A
Unit
55
70
Min.
Max.
Min.
Max.
t
AVAV
Read Cycle Time
55
70
ns
t
AVQV
Address Valid to Output Valid
55
70
ns
t
AXQX (1)
Data hold from address change
5
5
ns
t
EHQZ
(2,3)
Chip Enable High to Output Hi-Z
20
25
ns
t
ELQV
Chip Enable Low to Output Valid
55
70
ns
t
ELQX (1)
Chip Enable Low to Output Lo-Z
5
5
ns
t
GHQZ (2,3)
Output Enable High to Output Hi-Z
20
25
ns
t
GLQV
Output Enable Low to Output Valid
25
35
ns
t
GLQX (1)
Output Enable Low to Output Transition
5
5
ns
t
PD (4)
Chip Enable High to Power Down
55
70
ns
t
PU (4)
Chip Enable Low to Power Up
0
0
ns
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