參數(shù)資料
型號(hào)： M68AF031AM55MS6E
廠商： 意法半導(dǎo)體
英文描述： 256 Kbit (32K x 8) 5.0V Asynchronous SRAM
中文描述： 256千位（32K的× 8）5.0V異步SRAM
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 383K
代理商： M68AF031AM55MS6E
M68AF031A
14/22
Table 8. Write Mode AC Characteristics
Note: 1. At any given temperature and voltage condition, t
WLQZ
is less than t
WHQX
for any given device.
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
Figure 15. Low V
CC
Data Retention AC Waveforms
Symbol
Parameter
M68AF031A
Unit
55
70
Min.
Max.
Min.
Max.
t
AVAV
Write Cycle Time
55
70
ns
t
AVEH
Address Valid to Chip Enable High
45
60
ns
t
AVEL
Address valid to Chip Enable Low
0
0
ns
t
AVWH
Address Valid to Write Enable High
45
60
ns
t
AVWL
Address Valid to Write Enable Low
0
0
ns
t
DVEH
Input Valid to Chip Enable High
25
30
ns
t
DVWH
Input Valid to Write Enable High
25
30
ns
t
EHAX
Chip Enable High to Address Transition
0
0
ns
t
EHDX
Chip enable High to Input Transition
0
0
ns
t
ELEH
Chip Enable Low to Chip Enable High
45
60
ns
t
ELWH
Chip Enable Low to Write Enable High
45
60
ns
t
WHAX
Write Enable High to Address Transition
0
0
ns
t
WHDX
Write Enable High to Input Transition
0
0
ns
t
WHQX (1)
Write Enable High to Output Transition
5
5
ns
t
WLEH
Write Enable Low to Chip Enable High
45
60
ns
t
WLQZ (1,2)
Write Enable Low to Output Hi-Z
20
25
ns
t
WLWH
Write Enable Low to Write Enable High
45
50
ns
AI05925
DATA RETENTION MODE
tR
5.5V
tCDR
VCC 4.5V
VDR > 2.0V
E
E
≥
VDR – 0.2V
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