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| 型號(hào)： | M66596WG |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 106/133頁(yè) |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 72 of 127
3.3 Pipe control
Table 3.11 shows the pipe setting items of the controller. With USB data transfers, data communication has to be
carried out using the logic pipe called the end point. This controller has eight pipes that are used for data transfers.
Settings should be entered for each of the pipes in conjunction with the specifications of the user system.
Table 3.11 Pipe setting items
Register
name
Bit name
Setting contents
Note
TYPE
Specifies the transfer
type
Please refer to Chapter
BFRE
Selects the BRDY
interrupt mode
PIPE1-5: Can be set
Please refer to Chapters 3.4.3.5
DBLB
Selects a single or double
buffer
PIPE1-5: Can be set
Please refer to Chapter 3.4.1.5
CNTMD
Selects continuous
transfer or
non-continuous transfer
DCP: Can be set
PIPE1-2: Can be set (can be set only when bulk transfer has
been selected)
PIPE3-5: Can be set
With continuous transmission and reception, the buffer size
should be set to an integer multiple of the payload.
Please refer to Chapter 3.4.1.6
DIR
Selects transfer direction
(reading or writing)
IN or OUT can be set.
Please refer to Chapter 3.4.2.1
(DCP is controlled by ISEL).
EPNUM
End point number
Please refer to Chapter
DCPCFG
PIPECFG
SHTNAK
Selects disabled state for
pipe when transfer ends
PIPE1-2: Can be set (can be set only when bulk transfer has
been selected)
PIPE3-5: Can be set
Please refer to Chapter
BUFSIZE
Buffer memory size
DCP: Cannot be set (fixed at 256 bytes)
PIPE1-5: Can be set (can be specified up to a maximum of 2
KB in 64-byte units)
PIPR6-7: Cannot be set (fixed at 64 bytes)
Please refer to Chapter 3.4.1
PIPEBUF
BUFNMB
Buffer memory number
DCP: Cannot be set (areas fixed at 0-3)
PIPE1-5: Can be set (can be specified in areas 6-4F)
PIPE6-7: Cannot be set (areas fixed at 4-5)
Please refer to Chapter 3.4.1.
DCPMAXP
PIPEMAXP
MXPS
Maximum packet size
Please refer to Chapter
IFIS
Buffer Flush
PIPE1-2: Can be set (only when isochronous transfer has been
selected)
PIPE3-7: Cannot be set
Please refer to Chapter 3.9.5.
PIPEPERI
IITV
Interval Counter
PIPE1-2: Can be set (only when isochronous transfer has been
selected)
PIPE3-7: Cannot be set
Please refer to Chapter 3.9.3.
BSTS
Buffer Status
Please refer to Chapter 3.4.1.1
(also related to DIR / ISEL)
INBUFM
IN Buffer Monitor
Please refer to Chapter 3.4.1.1
(also related to DIR / ISEL)
ACLRM
Auto Buffer Clear
Enabled / disabled setting can be set when buffer memory
reading is set.
Please refer to Chapter 3.4.1.4
SQCLR
Sequence Clear
Clears the data toggle bit.
Please refer to Chapter
SQSET
Sequence Set
Sets the data toggle bit.
Please refer to Chapter
SQMON
Sequence Confirm
Confirms the data toggle bit.
Please refer to Chapter
DCPCTR
PIPExCTR
PID
Response PID
Please refer to Chapter
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