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參數(shù)資料
| 型號： | M65675FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | DIGITAL NTSC/PAL ENCODER |
| 中文描述： | 數(shù)字的NTSC / PAL編碼器 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 83K |
| 代理商： | M65675FP |
MITSUBISHI ICs (TV)
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
9
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
Composite-sync Generation
The timing-corrected c-sync signal, for an addition to the Y signal, is
generated in accordance with RS170A (NTSC) and CCIR (PAL)
standards, as shown in fig. 4.
9 cycles
set-up
7.5
±
2
-40
0
100
90
133
IRE
4
0
H
(reference point)
10.9
±
0.2
μ
s
20
19 cycles
0
63
106127
837
72
858
0
31
460
366
795
0
429
429
cycle counts (13.5MHz)
peak level including chroma signal
white peak level
cycle counts (13.5MHz)
9.4
±
0.1
μ
s
4.7
±
0.1
μ
s
1.5
±
0.1
μ
s
0.14
±
0.1
μ
s
40
±
2
0.714V
0.286V
0.14
±
0.2
μ
s
2.3
±
0.1
μ
s
31.7775
μ
s
0.14
±
0.2
μ
s
0.14
±
0.2
μ
s
0.14
±
0.2
μ
s
4.7
±
0.1
μ
s
27.1
μ
s
31.7775
μ
s
Fig. 4-1 NTSC HORIZONTAL SYNC SIGNAL (referred to EIARS170A)
Equalizing pulse
Serrated pulse
set-up
0-2
-43
0
100
90
133
IRE
10
0
H
(reference point)
12
±
0.3
μ
s
50
0
63
107142
844
76
864
0
32
464
368
800
0
432
432
cycle counts (13.5MHz)
peak level including chroma signal
white peak level
cycle counts (13.5MHz)
5.6
±
0.1
μ
s
4.7
±
0.2
μ
s
1.5
±
0.3
μ
s
0.2
±
0.1
μ
s
43
±
10%
0.7V
0.3V
0.2
±
0.1
μ
s
2.35
±
0.1
μ
s
62.0
μ
s
0.2
±
0.1
μ
s
4.7
±
0.2
μ
s
27.3
μ
s
62.0
μ
s
0.3
±
0.1
μ
s
10
±
1cycles
Equalizing pulse
Serrated pulse
0.2
±
0.1
μ
s
0.2
±
0.1
μ
s
Fig. 4-2 PAL HORIZONTAL SYNC SIGNAL (referred to CCIR)
Serial Interface
The M65675FP/M65676FP has a serial data receiver, in
compliance with both typical and high speed modes, based on I
2
C
serial bus specification. The slave-address of it also responds to
two addresses of 40h and 42h. The address setting is done by
following procedure;
address setting pin DVASEL (pin 3) is "L" and "H" for the address of
40h and 42h, respectively.
The serial data are stored in the data register in the serial interface
block according to the appointed address after the receipt of the
data. The stored data will be loaded to the registers in each internal
blocks at the timing of the first trailing edge of V-sync after the
transmission flag (WE) have been set up.
Analog Blocks
D-A Converter
The M65675FP/M65676FP has two 10-bit D-A converters. A
reference current of the D-A converters is supplied directly through
the Yref and Cref pins. The power save mode cuts the circuit
current. The maximum output amplitude is 1.2V
P-P
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| M65727FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:MPEG2 MOTION ESTIMATION LSI |
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