參數(shù)資料
型號(hào): M62320GP
元件分類: 微控制器/微處理器
英文描述: 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封裝: 4.40 X 5 MM, 0.65 MM PITCH, PLASTIC, SSOP-16
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 136K
代理商: M62320GP
M62320GP
REJ03D0909-0100 Rev.1.00 Mar 25, 2008
Page 4 of 10
I
2C BUS Characteristics
Limits
Item
Symbol
Min
Max
Unit
SCL clock frequency
fSCL
0
100
kHz
Free time: the bus must be free before a new transmission can start
tBUF
4.7
μs
Hold time START Condition
After this period, the first clock pulse is generated.
tHD:STA
4.0
μs
Low period of the clock
tLOW
4.7
μs
High period of the clock
tHIGH
4.0
μs
Set-up time for START condition
Only relevant for a repeated START condition
tSU:STA
4.7
μs
Data Hold time
tHD:DAT
0
μs
Data Set-up time
tSU:DAT
250
ns
Rise time of SDA and SCL signals
tR
1000
ns
Fall time of SDA and SCL signals
tF
300
ns
Set-up time for STOP condition
tSU:STO
4.0
μs
Note:
Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Timing Chart
VIH
tBUF
tSU:STO
tSU:STA
tHD:DAT
tSU:DAT
tHD:STA
Start
Stop
tHIGH
tLOW
tR, tF
VIL
SDA
VIH
VIL
SCL
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