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參數(shù)資料
| 型號： | M62320FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
| 封裝： | 5.30 X 10.10 MM, 1.27 MM PITCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大小： | 165K |
| 代理商： | M62320FP |
M62320P/FP
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 6 of 10
Digital Data Format
1. Write mode: I
2C BUS data input to parallel data output
First
Last
S
Slave address
W
A
I/O setting
A
8-bit data
A
8-bit data
A
…..
A
P
2. Read mode: Parallel data input to I
2C BUS data output
First
Last
S
Slave address
W
A
8-bit data
A
8-bit data
A
8-bit data
A
…..
8-bit data
A
P
Transmission from Master (MCU etc.) to Slave (M62320)
Transmission from Slave (M62320) to Master (MCU etc.)
S: Start condition
While SCL level is high, SDA line level should be changed from high to low.
Slave address
Chip select data
MSB
LSB
A2
A1
A0
CS2
CS1
CS0
0
1
A2
A1
A0
First
MSB
Last
LSB
0
L
0
1
L
H
0
1
0
L
H
L
:
1
H
Note:
Lower three bits (A0, A1, A2) are a programmable
address. This IC is accessed only when the lower 3
bits data of slave address coincide with the data of
CS0 to CS2. (refer to the right table)
Note: L = Low, H = High
W: Write (SDA = Low), R: Read (SDA = High)
A: Acknowledge bit
I/O setting data (I/O setting of parallel data I/O terminals.)
P7
P1
P6
P5
P4
P3
P2
First
MSB
Last
LSB
P0
Note:
DATA INPUT from parallel data terminals = Low
DATA OUTPUT to parallel data terminals = High
Each bit data corresponds to the I/O state of the parallel data terminals.
8-bit data
D7
D1
D6
D5
D4
D3
D2
First
MSB
Last
LSB
D0
P: Stop condition
While SCL level is high, SDA level should be changed from low to high.
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|---|---|
| M62320FP#DF5G | 制造商:Renesas Electronics Corporation 功能描述: |
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| M62320P | 制造商:Renesas Electronics Corporation 功能描述: |
| M62332FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-bit 2ch I2C BUS D/A Converter with Buffer Amplifiers |
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