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參數(shù)資料
| 型號： | M62023P |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP |
| 中文描述： | 系統(tǒng)復(fù)位IC具有內(nèi)存背面的開關(guān)，向上 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 47K |
| 代理商： | M62023P |
MITSUBISHI <Dig./Ana.INTERFACE>
M62023L,P,FP
1997.5.30- rev
( / )
PRELIMINARY
Some parametric limits are subject to change.
TIMING CHART
V
1
=V
IN
-V
DROP
V
2
=V
IN
-V
EB(SW Tr.)
V
3
=V
BAT
-V
F
V
SH
V
SL
V
S
3V
t
pd
t
pd
V
IN
0V
V
OUT
V
1
V
2
V
3
V
2
V
3
3V
V
IN(V
SL
)
V
OL(CS)
V
OL(RES)
V
OL(RES)
V
IN(V
SL
)
V
OH(RES)
CS
RES
RES
As the state shifts from a logic
high to logic low, the output
level becomes V
OL(RES)
The output level is V
OL(CS)
with a logic low
The output level is V
OH(RES)
with a logic high
In normal operation
Input voltage : 3V
Input
voltage
V
OUT
RES
CS
RES
Output
pin
With SW Tr. set to ON, a
voltage (V
IN
-V
DROP
) is output
The output level is V
with a logic low
In failure
(instantaneous drop)
Input voltage : 3V 2V
Each output varies if the input
voltage drops to V
SL
or under
SW Tr. is turned OFF. A
voltage (V
IN
-V
EB
) is output by
the diode between E and B of
SW Tr.
As the state shifts from a logic
low to logic high, the output
level becomes approximately
equal to the input voltage
Restoration from failure
(instantaneous drop)
Input voltage : 2V 3V
If the input voltage goes higher
than V
SL
by 100mV, each
output varies after delay
produced by the delay circuit
SW Tr. is turned ON after delay
and a voltage (V
IN
-V
DROP
) is
output
A logic high is maintained, and
then shifts to a logic low
In backup state
Input voltage : 0V
Backup voltage : 3V
V
BAT
-V
F
The output is a logic high and
the output level is V
BAT
-V
F
As the state shifts from a logic
low to logic high, the output
level becomes the voltage
V
IN
-V
EB
A logic low is maintained, and
then shifts to a logic high
A logic high is maintained, and
then shifts to a logic low
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