參數(shù)資料
型號(hào)： M5M5Y5636TG-25
廠商： Mitsubishi Electric Corporation
英文描述： 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
中文描述： 18874368位（524288 - Word的36位）網(wǎng)絡(luò)的SRAM
文件頁(yè)數(shù)： 20/27頁(yè)
文件大小： 212K
代理商： M5M5Y5636TG-25
MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
20
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and
TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is
placed in the Test-Logic-Reset state.
Bypass Register
The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed
through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The Boundary Scan
Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits
in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the
TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the Capture-RD state and then is placed
between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST
instruction can be used to activate the Boundary Scan Register.
Identification (ID) Register
The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the Capture-DR
state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It describes various
attributes of the SRAM (see page 25). The register is then placed between the TDI and TDO pins when the controller is moved into the
Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in
prescribed ways. Although the TAP Controller in this device follows the 1149.1 conventions, it is not 1194.1-compliant because one of
the mandatory instructions, EXTEST, is uniquely implemented. The TAP on this device may be used to monitor all input and I/O pads.
This device will not perform INTEST but can perform the preload portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in the Capture-IR state, the two least significant bits of the instruction register are loaded with 01.
When the TAP controller is moved to the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state the
desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction
Set for this device is listed in the following table.
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This
occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the
Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the
Boundary Scan Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the
default state identified in the BSDL file. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to
attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to
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