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參數(shù)資料
| 型號： | M5M5Y5636TG-22 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網(wǎng)絡的SRAM |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 212K |
| 代理商： | M5M5Y5636TG-22 |
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
8
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
DC OPERATED TRUTH TABLE
Name
Input Status
HIGH or NC
LOW
Operation
Interleaved Burst Sequence
Linear Burst Sequence
LBO#
Note5. LBO# is DC operated pin.
Note6. NC means No Connection.
Note7. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
(1) Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
A18~A2
A18~A2
latched A18~A2
latched A18~A2
latched A18~A2
A1,A0
0 , 0
0 , 1
1 , 0
1 , 1
0 , 1
0 , 0
1 , 1
1 , 0
1 , 0
1 , 1
0 , 0
0 , 1
1 , 1
1 , 0
0 , 1
0 , 0
(2) Linear Burst Sequence (when LBO# = LOW)
Operation
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
Note8. The burst sequence wraps around to its initial state upon completion.
A18~A2
A18~A2
latched A18~A2
latched A18~A2
latched A18~A2
A1,A0
0 , 0
0 , 1
1 , 0
1 , 1
0 , 1
1 , 0
1 , 1
0 , 0
1 , 0
1 , 1
0 , 0
0 , 1
1 , 1
0 , 0
0 , 1
1 , 0
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