參數(shù)資料
型號(hào)： M5M5V416BWG-85LW
廠商： Mitsubishi Electric Corporation
英文描述： 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
中文描述： 4194304位（262144字由16位）的CMOS靜態(tài)RAM
文件頁(yè)數(shù)： 4/11頁(yè)
文件大小： 110K
代理商： M5M5V416BWG-85LW
MITSUBISHI ELECTRIC
M5M5V416BTP,RT
revision-P04, ' 98.12.16
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Some parametric limits are subject to change
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Input rise time and fall time
Reference level
Output loads
2.7V~3.6V
V
IH
=2.4V,V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Transition is measured ±500mV from
steady state voltage.(for t
en
,t
dis
)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Supply voltage
Input pulse
1TTL
CL
DQ
Fig.1 Output load
Including scope and
jig capacitance
t
CR
t
a
(A)
ns
ns
ns
ns
t
a
(S1)
t
a
(S2)
t
a
(OE)
t
dis
(S1)
t
dis
(S2)
t
dis
(OE)
t
en
(S1)
t
en
(S2)
t
en
(OE)
t
V
(A)
10
10
70L,70H,70LW
70HW,70LI,70HI
Min
45
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
a
(BC1)
t
a
(BC2)
t
dis
(BC1)
t
dis
(BC2)
t
en
(BC1)
t
en
(BC2)
ns
ns
ns
ns
85
85
85
85
85
30
30
30
10
10
5
10
100
10
10
50
35
35
100
100
100
100
100
35
35
35
10
10
5
10
70
85
10
10
10
10
10
35
25
25
70
70
70
70
70
25
25
25
85L,85H,85LW
85HW,85LI,85HI
Min
10L,10H,10LW
10HW,10LI,10HI
Min
4
t
su
(A-WH)
t
su
(BC1)
t
su
(BC2)
t
CW
t
w
(W)
t
su
(A)
t
su
(S1)
t
su
(S2)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
ns
ns
ns
ns
ns
ns
ns
ns
70
55
0
65
65
65
65
65
ns
ns
ns
ns
ns
ns
ns
25
25
5
5
35
0
0
35
35
70L,70H,70LW
70HW,70LI,70HI
Min
85L,85H,85LW
85HW,85LI,85HI
Min
10L,10H,10LW
10HW,10LI,10HI
Min
30
30
100
75
0
85
85
85
85
85
5
5
40
0
0
85
60
0
70
70
70
70
70
5
5
35
0
0
Symbol
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S1 high
Limits
Output disable time after S2 low
Output disable time after BC1 high
Output disable time after BC2 high
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after BC1 low
Output enable time after BC2 low
Output enable time after OE low
Data valid time after address
(3) WRITE CYCLE
Max
Max
Max
Units
(2) READ CYCLE
Max
Max
Max
Limits
Units
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Symbol
Parameter
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