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參數(shù)資料
| 型號(hào)： | M5M5V32R16J-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| 中文描述： | 524288位（32768字由16位）的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | M5M5V32R16J-10 |
M5M5V32R16J,TP-10,-12,-15
MITSUBISHI LSIs
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
1
Outline
44P0K(J)
44P3W-H(TP)
PIN CONFIGURATION (TOP VIEW)
1997.01.22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FEATURES
Fast access time M5M5V32R16J,TP-10 10ns(max)
M5M5V32R16J,TP-12 12ns(max)
M5M5V32R16J,TP-15 15ns(max)
Low power dissipation Active 297mW(typ)
Stand by 0.33mW(typ)
Single +3.3V power supply
Fully static operation : No clocks, No refresh
Common data I/O
Easy memory expansion by /S
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Directly TTL compatible : All inputs and outputs
Separate control of lower and upper bytes by /LB and /UB
DESCRIPTION
The M5M5V32R16 is a family of 32768-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 3.3V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by /LB
and /UB.
APPLICATION
High-speed memory system
DQ
1
DQ
2
DQ
3
DQ
4
Vcc
GND
DQ
5
DQ
6
DQ
7
DQ
8
/W
A14
A13
A12
A11
NC
M
ADDRESS
INPUTS
CHIP
SELECT
INPUTS
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
OUTPUTS
WRITE
CONTROL
INPUT
ADDRESS
INPUTS
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
OUTPUTS
BYTE
CONTROL
INPUTS
ADDRESS
INPUTS
1
N.C
A3
A2
A1
A0
/S
FUNCTION
The operation mode of the M5M5V32R16 is
determined by a combination of the device control
inputs /S, /W, /OE, /LB, and /UB. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with low level /LB and/or low level /UB and low
level /S. The address must be set-up before write cycle
and must be stable during the entire cycle. upper-Byte are in a non-selectable mode.
The data is latched into a cell on the traling edge of
/W, /LB, /UB or /S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input /OE directly
controls the output stage. Setting the /OE at a high
level, the output stage is in a high impedance state, and
the data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and /OE at a low level while /LB and/or /UB and /S are
in an active state. (/LB and/or /UB=L, /S=L)
When setting /LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting /UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and
When setting /LB and /UB at a high level or /S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by /LB, /UB and /S.
Signal-/S controls the power-down feature. When /S
goes high, power dissapation is reduced extremely.
The access time from /S is equivalent to the address
access time.
PACKAGE
M5M5V32R16J : 44pin 400mil SOJ
M5M5V32R16VP: 44pin 400mil TSOP(II)
2
3
4
5
6
7
8
9
10
11
12
(3.3V)
(0V)
13
14
15
16
17
18
19
20
21
22
DQ
16
DQ
15
DQ
14
DQ
13
GND
Vcc
DQ
12
DQ
11
DQ
10
DQ
9
NC
A7
A8
A9
A10
NC
A4
A5
A6
/OE
/UB
/LB
35
34
33
32
31
30
29
28
27
26
25
24
23
36
35
38
39
40
41
42
43
44
OENABLE
(0V)
(3.3V)
相關(guān)PDF資料 |
PDF描述 |
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| M5M5V32R16J-12 | 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16J-15 | 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16VP-10 | 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16VP-12 | 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16VP-15 | 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5V32R16J-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16J-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16VP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16VP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V32R16VP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
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