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參數(shù)資料
| 型號(hào)： | M5M5V208VP-12LL-W |
| 廠(chǎng)商： | Mitsubishi Electric Corporation |
| 英文描述： | 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM |
| 中文描述： | 2097152位（262144 - Word的8位）的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 88K |
| 代理商： | M5M5V208VP-12LL-W |
MITSUBISHI LSIs
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5V208FP,VP,RV,KV,KR
-70L-W , -85L -W, -10L-W , -12L-W ,
-70LL-W, -85LL-W, -10LL-W, -12LL-W
'97.3.21
6
Write cycle ( S
1
control mode)
Write cycle (S
2
control mode)
t
su
(S1)
(Note 3)
(Note 3)
t
rec
(W)
t
h
(D)
t
CW
(Note 5)
(Note 3)
(Note 3)
t
su
(A)
(Note 4)
t
su
(D)
t
h
(D)
t
CW
(Note 5)
(Note 3)
(Note 3)
t
su
(S2)
t
rec
(W)
t
su
(A)
(Note 4)
(Note 3)
(Note 3)
t
su
(D)
DATA IN
STABLE
DATA IN
STABLE
DQ
1~8
S
1
S
2
W
A
0~17
DQ
1~8
S
1
S
2
W
A
0~17
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5V208VP-12L-W | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5V208VP-70L | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5V208VP-70LL | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5V208VP-70LL-W | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5V208VP-70L-W | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM |
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