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參數(shù)資料
| 型號： | M5M5256DFP-70LLI#SM |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 0.450 INCH, LEAD FREE, SOP-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 160K |
| 代理商： | M5M5256DFP-70LLI#SM |
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
6
Write cycle ( /S control mode)
t
su
(S)
t
rec
(W)
t
h
(D)
t
CW
(Note 5)
(Note 3)
(Note 3)
t
su
(A)
(Note 4)
t
su
(D)
DATA IN
STABLE
DQ
1~8
/S
/W
A
0~14
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed in overlap of /S and /W low.
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
7 : ten, tdis are periodically sampled and are not 100% tested.
(4) MEASUREMENT CONDITIONS
Input pulse level .............. V
IH
=2.4V,V
IL
=0.6V
Input rise and fall time ..... 5ns
Reference level ................ V
OH
=V
OL
=1.5V
Output load ...................... Fig.1 CL=50pF (-55LL,-55XL )
CL=100pF (-70LL,-70LLI,-70XL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Vcc
DQ
C
L
Fig.1 Output load
1.8k
990
(Including
scope and JIG)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5256DFP-70LLITR | 制造商:Renesas Electronics Corporation 功能描述:ASYNCH SRAM 256KB 32KX8 70NS SOP28 INDUSTRIAL TEMP - Tape and Reel |
| M5M5256DFP-70VLL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DFP-70VLL-I | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DFP-70VLL-W | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DFP-70VXL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
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