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參數(shù)資料
| 型號(hào)： | M5M5256DFP-70LL |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-PDIP -40 to 85 |
| 中文描述： | 262144位（32768 - Word的8位）的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | M5M5256DFP-70LL |
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -70VLL,-85VLL,
-70VXL,-85VXL
'97.4.7
FUNCTION
The operation mode of the M5M5256DP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table. When setting /S at a high level, the chip is in a
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
FUNCTION TABLE
Mode
DQ
Icc
/S
/W
/OE
Non selection
Write
Read
Stand-by
Active
Active
Active
High-impedance
D
IN
D
OUT
X
X
L
L
L
L
X
L
H
H
H
H
High-impedance
2
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
VCC
(3.3V)
GND
27
20
22
2
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
12
11
13
15
16
17
18
19
A
B
R
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
S
O
D
B
C
D
A
B
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
/OE
/S
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
DATA I/O
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
CHIP SELECT
INPUT
BLOCK DIAGRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M5256DFP-70VLL-W | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DVP-85VLL | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DVP-85VLL-I | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DVP-85VXL | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DFP-70VLL-I | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5256DFP-70LL#BM | 制造商:Renesas Electronics 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SOP 制造商:Renesas Electronics 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SOP Bulk 制造商:Renesas Electronics Corporation 功能描述:IC SRAM 256K 5M5256 SOP28 |
| M5M5256DFP-70LLI | 制造商:Mitsubishi Electric 功能描述:32K X 8 STANDARD SRAM, 70 ns, PDSO28 制造商:Renesas Electronics Corporation 功能描述:32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| M5M5256DFP-70LLI#BM | 制造商:Renesas Electronics Corporation 功能描述:M5M5256DFP-70LLI#BM - Tape and Reel |
| M5M5256DFP-70LLI(#BM) | 制造商:Renesas Electronics Corporation 功能描述: |
| M5M5256DFP-70LLIBM | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SOP |
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