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參數(shù)資料
| 型號(hào)： | M5M5255DP-45XL |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| 中文描述： | 262,144位（32,768字8位）的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 64K |
| 代理商： | M5M5255DP-45XL |
MITSUBISHI LSIs
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5255DP,FP -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
FUNCTION
The operation mode of the M5M5255DP,FP is determined
by a combination of the device control inputs /S1, S2 and
/W. Each mode is summarized in the function table. When setting /S1 at a high level or S2 at a low level, the
A write cycle is executed whenever the low level /W
overlaps with the low level /S1 and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of /W, /S1 or S2, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained.
FUNCTION TABLE
2
A read cycle is executed by setting /W at a high level
while /S1 and S2 are in an active state(/S1="L", S2="H").
chip is in a non-selectable mode in which both reading and
writing are disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S1 and S2. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the
non-selected mode.
Mode
DQ
Icc
/S1
S2
Non selection
Write
Read
Stand-by
Active
Active
D
IN
D
OUT
X
L
L
L
L
H
H
H
High-impedance
/W
X
X
L
H
Non selection
High-impedance
Stand-by
VCC
GND
27
20
22
2
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
12
11
13
15
16
17
18
19
A
B
R
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
S
O
D
B
C
D
A
B
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
S2
/S1
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
DATA I/O
WRITE CONTROL
INPUT
CHIP SELECT
INPUT1
FUNCTION TABLE
CHIP SELECT
INPUT2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M5255DP-55LL | 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255DP-55XL | 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255DP-70LL | 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255DP-70XL | 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255FP-45LL | 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5255DP-55LL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255DP-55XL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255DP-70LL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255DP-70XL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5255FP-45LL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM |
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