參數(shù)資料
型號(hào): M5M51R16AWG-15L
廠商: Mitsubishi Electric Corporation
英文描述: 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
中文描述: 1048576位(65536字由16位)的CMOS靜態(tài)RAM
文件頁(yè)數(shù): 6/7頁(yè)
文件大?。?/td> 84K
代理商: M5M51R16AWG-15L
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
M5M51R16AWG -10L, -12L, -15L,
-10H, -12H, -15H
MITSUBISHI
ELECTRIC
Aug.1. 1998
Note 4: Hatching indicates the state is "don't care".
Note 5: Writing is executed while S low overlaps BC1 and/or BC2 low and W low.
Note 6: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2
or falling edge of S, the outputs are maintained in the high impedance state.
Note 7:Don't apply inverted phase signal externally when DQ pin is output mode.
Note 8:
t
en,
t
dis are periodically sampled and are not 100% tested.
Note 9:
t
CR(Read cycle time) is defined as whole time from reading address set up to this address change
under read mode set condition by S,W,OE,BC1 and/or BC2.
Note 10:
t
CW(Write cycle time) is defined as whole time from writing address set up to this address change
under write mode set condition by S,W,BC1 and/or BC2.
Write cycle ( BC1, BC2 control mode )
6
DQ1~16
BC1 and/or BC2
t
su(BC1) or
t
su(BC2)
S
(Note 4)
(Note 4)
A0~15
W
t
rec(W)
t
h(D)
t
CW
DATA IN
STABLE
(Note 6)
(Note 4)
(Note 4)
t
su(A)
(Note 5)
t
su(D)
Write cycle (S control mode)
DQ1~16
BC1 and/or BC2
S
A0~15
W
t
h(D)
t
CW
DATA IN
STABLE
(Note 6)
(Note 4)
(Note 4)
t
su(S)
t
rec(W)
t
su(A)
(Note 5)
(Note 4)
(Note 4)
t
su(D)
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