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參數(shù)資料
| 型號(hào)： | M5M51008DRV-70H |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | DRAM |
| 英文描述： | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| 中文描述： | 1048576位（131072 - Word的8位）的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 61K |
| 代理商： | M5M51008DRV-70H |
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
1997-3/25
MITSUBISHI
ELECTRIC
6
Write cycle ( S
1
control mode)
Write cycle (S
2
control mode)
t
su (S1)
(Note 3)
(Note 3)
t
rec (W)
t
h (D)
t
CW
(Note 5)
(Note 3)
(Note 3)
t
su (A)
(Note 4)
t
su (D)
t
h (D)
t
CW
(Note 5)
(Note 3)
(Note 3)
t
su (S2)
t
rec (W)
t
su (A)
(Note 4)
(Note 3)
(Note 3)
t
su (D)
DATA IN
STABLE
DATA IN
STABLE
DQ
1~8
S
1
S
2
W
A
0~16
DQ
1~8
S
1
S
2
W
A
0~16
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S
2
high overlaps S
1
and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S
1
or rising edge of S
2
, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
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| M5M51008BFP | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008DVP-55H | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008DVP-70H | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008BFP-10VL | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M51008DRV-70H(#BT) | 制造商:Renesas Electronics Corporation 功能描述: |
| M5M51008DRV-70HIA0 | 制造商:Renesas Electronics Corporation 功能描述:128 X 8 1M LP SRAM REVERSED TS |
| M5M51008DVP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008DVP-55H | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008DVP-55H#ST | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 55ns 32-Pin TSOP-I T/R |
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