參數(shù)資料
型號(hào)： M5M4V64S20ATP-8
廠商： Mitsubishi Electric Corporation
英文描述： 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
中文描述： 64M號(hào)（4銀行甲4194304字× 4位）同步DRAM
文件頁數(shù)： 19/48頁
文件大?。?/td> 1097K
代理商： M5M4V64S20ATP-8
M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the
data output. The terminated banl remains active. READ to TERM interval is minimum 1 CLK. A TERM
command to output disable latency is equivalent to the /CAS Latency. As a result, READ to TERM interval
determines valid data length to be output. The figure below shows examples of BL=4.
Read Interrupted by Burst Terminate (BL=4)
CLK
CL=3
Command
DQ
READ
TERM
Q0
Q1
Q2
Command
DQ
READ
TERM
Q0
CL=2
Command
DQ
READ
TERM
Q0
Q1
Q2
Command
DQ
READ
TERM
Q0
Command
DQ
READ TERM
Q0
Q1
Command
DQ
READ TERM
Q0
Q1
19
相關(guān)PDF資料
PDF描述
M5M4V64S20ATP-8A 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8L 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M51008KR-10L 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M51008KR-10LL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M51008KR-55L 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V64S20ATP-8A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S30ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-10L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-12 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
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