參數(shù)資料
型號: M5M465800DTP-5S
廠商: Mitsubishi Electric Corporation
英文描述: FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
中文描述: 快速頁面模式67108864位(16777216 - Word的4位)動態(tài)隨機存儲器
文件頁數(shù): 9/37頁
文件大?。?/td> 362K
代理商: M5M465800DTP-5S
MITSUBISHI
ELECTRIC
Jun. 1999
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.1)
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
9
SWITCHING CHARACTERISTICS
(Ta=0 70 C
±
Parameter
Symbol
Limits
Unit
M5M46X400B-5,5S
M5M46X800B-5,5S
M5M465160B-5,5S
M5M46X400B-6,6S
M5M46X800B-6,6S
M5M465160B-6,6S
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
t
CAC
t
RAC
t
AA
t
CPA
ns
ns
ns
ns
ns
15
60
30
35
13
50
25
30
t
OEA
t
CLZ
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 7)
Access time from OE
Output low impedance time from CAS low
15
13
Min
Max
Min
Max
t
OEZ
(Note 12)
Output disable time after OE high
15
13
ns
t
OFF
13
15
ns
(Note 12)
Output disable time after CAS high
5
0
0
5
0
0
ns
Note 6: An initial pause of 500μs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are VOH=2.0V and VOL=0.8V.
8: Assumes that t
RCD
t
RCD(max)
and t
ASC
t
ASC(max)
and
t
CP
t
CP(max).
9: Assumes that t
RCD
t
RCD(max)
and t
RAD
t
RAD(max).
If t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will increase by amount that t
RCD
exceeds the value shown.
10: Assumes that t
RAD
t
RAD(max)
and t
ASC
t
ASC(max).
11: Assumes that t
CP
t
CP(max)
and t
ASC
t
ASC(max).
12: t
OFF(max)
and
t
OEZ(max)
defines the time at which the output achieves the high impedance state (I
OUT
10 A) and is not reference
to V
OH(min)
or
V
OL(max).
μ
C
Limits
Typ
Min
Max
5
Unit
pF
pF
pF
pF
pF
pF
Input capacitance,address inputs
Input capacitance, OE input
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
C
I (A)
C
I (OE)
C
I (W)
C
I (RAS)
C
I (CAS)
C
I / O
Symbol
Parameter
Test conditions
7
7
7
7
V
I
=Vss
f=1MH
Z
Vi=25mVrms
7
CAPACITANCE
(Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted)
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