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參數(shù)資料
| 型號： | M5M44800CJ-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| 中文描述： | 快速頁面模式4194304位（524288 - Word的8位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 202K |
| 代理商： | M5M44800CJ-6 |
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44800CJ,TP-5,-5S:Under development
Definition of CBR burst refresh
The CBR burst refresh performs more than 1024 continuous
CBR cycles within 16.4ms.
Definition of RAS only burst refresh
All combination of nine row address signals (A
0
~A
9
) are
selected during 1024 continuous RAS only refresh cycles
within 16.4ms.
2.1 CBR burst refresh
Switching from read/write operation to self refresh operation.
The time interval t
NSB
from the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within 16.4ms.
Switching from self refresh operation to read/write operation.
The time interval t
SNB
from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the last CBR refresh cycle during read/write operation period
should be set within 16.4ms.
2. Burst refresh during Read/Write operation
(A) Timing diagram
Read/Write
Self Refresh
Read/Write
t
NSB
t
RASS
≥
100μs
t
SNB
last
refresh
cycles
first
refresh
cycles
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the first
RAS only refresh cycle during read/write operation period to
the falling edge of RAS signal at the start of self refresh
operation should be set within t
NSB
(shown in table 3).
Switching from self refresh operation to read / write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period
should be set within t
SNB
(shown in table 3).
RAS
refresh cycles
1023 cycles
refresh cycles
1023 cycles
(B) Definition of burst refresh
16.4ms
read/write cycles
RAS
refresh cycles
1024 cycles
2.2 RAS only burst refresh
21
Table 3
Read/Write Cycle
CBR burst
refresh
RAS only
burst refresh
Read/Write
Self Refresh
Self Refresh
Read/Write
t
NSB
+t
SNB
≤
16.4ms
t
SNB
≤
16.4ms
t
NSB
≤
16.4ms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M44800CJ-6S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
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| M5M44800CJ-7S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CTP-5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CTP-5S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
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