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參數(shù)資料
| 型號： | M5M44800CJ-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| 中文描述： | 快速頁面模式4194304位（524288 - Word的8位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 202K |
| 代理商： | M5M44800CJ-5 |
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44800CJ,TP-5,-5S:Under development
6
Write Cycle (Early Write and Delayed Write)
Write cycle time
RAS low pulse width
CAS low pulse width
8
(Note 23)
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write setup time before CAS low
0
CAS hold time after RAS low
RAS hold time after CAS low
10000
10000
10000
10000
90
50
13
50
13
13
13
8
13
0
10
0
110
60
15
60
15
15
15
10
10
15
0
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
15
20
20
15
0
130
70
20
70
20
15
20
0
t
WC
t
RAS
t
CAS
t
CSH
t
RSH
t
WCS
t
WCH
t
CWL
t
RWL
t
WP
t
DS
t
DH
t
OEH
Parameter
Symbol
Limits
Unit
Min
Max
M5M44800C-5,-5S M5M44800C-6,-6S
Min
Max
M5M44800C-7,-7S
Min
Max
Read-Write and Read-Modify-Write Cycles
13
15
20
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
(Note 22)
(Note 23)
(Note 23)
(Note 23)
55
0
35
80
50
55
49
0
31
68
43
126
86
49
86
10000
10000
10000
10000
150
100
100
70
0
45
95
60
70
10000
10000
180
120
120
t
RWC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
CWD
t
RWD
t
AWD
t
CWL
OE hold time after W low
t
OEH
Note 22:
t
RWC
is specified as
t
RWC(min)
=
t
RAC(max)
+
t
ODD(min)
+
t
RWL(min)
+
t
RP(min)
+4
t
T
.
Note
23:
t
WCS
,
t
CWD
,
t
RWD
and
t
AWD
and,
t
CPWD
are specified as reference points only. If
t
WCS
≥
t
WCS(min)
the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If
t
CWD
≥
t
CWD(min)
,
t
RWD
≥
t
RWD(min)
,
t
AWD
≥
t
AWD(min)
and
t
CPWD
≥
t
CPWD(min)
(for fast page
mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above
condition (delayed write) of the DQ (at access time and until CAS or OE goes back to V
IH
) is indeterminate.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
Limits
Unit
Min
Max
M5M44800C-5,-5S M5M44800C-6,-6S
Min
Max
M5M44800C-7,-7S
Min
Max
8
Data hold time after CAS low or W low
t
DH
Data setup time before CAS low or W low
t
DS
0
10
0
8
0
15
ns
ns
t
WP
10
8
15
ns
Write pulse width
13
15
20
RAS hold time after W low
t
RWL
ns
13
15
20
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| M5M44800CJ | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
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| M5M44800CTP-5S | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CTP-6 | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M44800CJ-5S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CJ-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CJ-6S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CJ-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CJ-7S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
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