參數(shù)資料
型號(hào)： M5M44260CJ-7
廠商： Mitsubishi Electric Corporation
英文描述： FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
中文描述： 快速頁面模式4194304位（262144字由16位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁數(shù)： 5/29頁
文件大小： 283K
代理商： M5M44260CJ-7
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44260CJ,TP-5,-5S : Under development
5
Read and Refresh Cycles
Note 21: Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
Limits
Min
90
50
13
50
13
Max
Parameter
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Symbol
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
t
OCH
t
ORH
Unit
Min
110
60
15
60
15
Max
Min
130
70
20
70
20
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low
(Note 21)
(Note 21)
10000
10000
10000
10000
10000
10000
0
0
0
25
13
13
0
0
0
30
15
15
0
0
0
35
20
20
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
Limits
Min
Max
8.2
128
Parameter
Refresh cycle time
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
Delay time, OE high to data
Symbol
t
REF
t
REF
Unit
Min
Max
8.2
128
Min
Max
8.2
128
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
DZO
t
CDD
t
ODD
(Note 19)
(Note 19)
(Note 20)
(Note 15)
(Note 16)
(Note 17)
ns
t
T
Transition time
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles)
(Ta=0~70C, V
CC
=5V±10%, V
SS
=0V, unless otherwise noted, see notes 6,13,14)
(Note 18)
(Note 18)
50
35
0
30
18
5
10
50
20
5
10
15
0
0
10
15
0
0
20
1
20
45
30
10
50
37
25
0
40
20
5
7
50
10
13
0
0
8
13
0
0
13
1
0
50
10
15
0
0
13
10
15
0
0
15
1
15
Note 13: The timing requirements are assumed
t
T
=5ns.
14: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
15:
t
RCD(max)
is specified as a reference point only. If
t
RCD
is less than
t
RCD(max)
, access time is
t
RAC
. If
t
RCD
is greater than
t
RCD(max
), access time is
controlled exclusively by
t
CAC
or
t
AA
.
16:
t
RAD(max)
is specified as a reference point only. If
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max
), access time is controlled exclusively by
t
AA
.
17:
t
ASC(max)
is specified as a reference point only. If
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
, access time is controlled exclusively by
t
CAC
.
18: Either
t
DZC
or
t
DZO
must be satisfied.
19: Either
t
CDD
or
t
ODD
must be satisfied.
20:
t
T
is measured between V
IH(min)
and V
IL(max)
.
M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M44260CJ-7S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CTP-5 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CTP-5S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CTP-6 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CTP-6S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
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