參數(shù)資料
型號(hào)： M5LV-320/192-10AC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： Fifth Generation MACH Architecture
中文描述： EE PLD, 10 ns, PBGA256
封裝： BGA-256
文件頁(yè)數(shù)： 43/47頁(yè)
文件大小： 1145K
代理商： M5LV-320/192-10AC
MACH 5 Family
5
Product-Term Array and Logic Allocator
The product-term array uses the same sum-of-products architecture as PAL devices and consists of
32 inputs (plus their complements) and 64 product terms arranged in 16
clusters. A cluster is a sum-
of-products function with either 3 of 4 product terms.
Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of
three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If
only three product terms in a cluster are steered, the fourth can be used as an input to an XOR
gate for separate logic generation and/or polarity control.
The
wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output
switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic
allocation scheme in the MACH 5 device allows for the implementation of large equations (up to
32 product terms) with only one pass through the logic array.
Table 4. Product Term Steering Options for PT Clusters and Macrocells
Macrocell
Available Clusters
Macrocell
Available Clusters
M0
C0, C1, C2, C3, C4
M8
C5, C6, C7, C8, C9, C10, C11, C12
M1
C0, C1, C2, C3, C4, C5
M9
C6, C7, C8, C9, C10, C11, C12, C13
M2
C0, C1, C2, C3, C4, C5, C6
M10
C7, C8, C9, C10, C11, C12, C13, C14
M3
C0, C1, C2, C3, C4, C5, C6, C7
M11
C8, C9, C10, C11, C12, C13, C14, C15
M4
C0, C1, C2, C3, C4, C5, C6, C7
M12
C8, C9, C10, C11, C12, C13, C14, C15
M5
C1, C2, C3, C4, C5, C6, C7, C8
M13
C9, C10, C11, C12, C13, C14, C15
M6
C2, C3, C4, C5, C6, C7, C8, C9
M14
C10, C11, C12, C13, C14, C15
M7
C3, C4, C5, C6, C7, C8, C9, C10
M15
C11, C12, C13, C14, C15
Block
Interconnect
Interconnect Feeder
Block
Feeder
32
I/Os
16
2
Macrocells
Logic
Alocator
Control Generator
OE Generator
Product-term
Array
32
Input Register
Path
2
Local
Feedback
20446G-002
Figure 2. PAL Block Structure
相關(guān)PDF資料
PDF描述
M5LV-320/192-10AI Fifth Generation MACH Architecture
M5LV-320/192-12AC Fifth Generation MACH Architecture
M5LV-320/192-12AI Fifth Generation MACH Architecture
M5LV-320/192-15AC Fifth Generation MACH Architecture
M5LV-320/192-15AI Fifth Generation MACH Architecture
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