1. C = Commercial grade, I = Industrial grade 2. /1 version recommended for new designs With Lattice" />
參數(shù)資料
型號： M5LV-128/104-7VI
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 23/42頁
文件大?。?/td> 0K
描述： IC CPLD 128MC 104I/O 144TQFP
標準包裝： 60
系列： MACH® 5
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 104
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
包裝： 托盤
MACH 5 Family
3
Note:
1.
C = Commercial grade, I = Industrial grade
2.
/1 version recommended for new designs
With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512 macrocells to
support full system logic integration. Extensive routing resources ensure pinout retention as well as high
utilization. It is ideal for PAL block device integration and a wide range of other applications including high-
speed computing, low-power applications, communications, and embedded control. At each macrocell density
point, Lattice offers several I/O and package options to meet a wide range of design needs (Table 3).
Note:
1.
The I/O options indicated with a “*” are obsolete, please contact factory for more information.
Advanced power management options allow designers to incrementally reduce power while maintaining the
level of performance needed for today’s complex designs. I/O safety features allow for mixed-voltage design,
Table 2. MACH 5 Speed Grades
Device
Speed Grade1
-5
-6
-7
-10
-12
-15
-20
M5-1282
C
C, I
I
M5-128/1
C
C, I
I
M5LV-128
C
C,I
C, I
I
M5-192/1
C
C, I
I
M5-2562
C
C, I
I
M5-256/1
C
C, I
I
M5LV-256
C
C, I
I
M5-320
C
C, I
I
M5LV-320
C
C, I
I
M5-384
C
C, I
I
M5LV-384
C
C, I
I
M5-512
C
C, I
I
M5LV-512
C
C, I
I
Table 3. MACH 5 Package and I/O Options 1
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Supply Voltage
5
3.3
5
3.3
5
3.3
5
3.3
5
3.3
100-pin TQFP
68
68, 74
68
68*, 74
100-pin PQFP
68
68*
68
144-pin TQFP
104
144-pin PQFP
104
104*
160-pin PQFP
120
120*
120
120*
120
120*
120
208-pin PQFP
160
240-pin PQFP
184*
256-ball BGA
192
192*
352-ball BGA
256
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關代理商/技術參數(shù)
參數(shù)描述
M5LV-256/104-10AC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10AI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10VC 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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