參數(shù)資料
型號(hào)： M58MR064C
廠(chǎng)商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù)： 8/52頁(yè)
文件大?。?/td> 399K
代理商： M58MR064C
M58MR064C, M58MR064D
16/52
Double Word Program (DPG)
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. The first command must be given to the
target block and only one partition can be pro-
grammed at a time; the other partition must be in
one of the read modes or in the erase suspended
mode (see Table 8).
The two words must differ only for the address A0.
Programming should not be attempted when VPP
is not at VPPH. The operation can also be executed
if VPP is below VPPH but result could be uncertain.
These instruction uses three write cycles. The first
command written is the Double Word Program
Set-Up command 30h. A second write operation
latches the Address and the Data of the first word
to be written, the third write operation latches the
Address and the Data of the second word to be
written and starts the P/E.C. (see Table 11).
Read operations in the targeted bank output the
Status Register content after the programming
has started. The Status Register bit b7 returns '0'
while the programming is in progress and '1' when
it has completed. After completion the Status reg-
ister bit b4 returns '1' if there has been a Program
Failure. Status register bit b1 returns '1' if the user
is attempting to program a protected block. Status
Register bit b3 returns a '1' if VPP is below VPPLK.
Any attempt to write a ’1’ to an already pro-
grammed bit will result in a program fail (status
register bit b4 set). (See Table 12).
Programming aborts if RP goes to VIL.Asdata in-
tegrity cannot be guaranteed when the program
operation is aborted, the memory location must be
erased and reprogrammed. A Clear Status Regis-
ter instruction must be issued to reset b5, b4, b3
and b1 of the Status Register. During the execu-
tion of the program by the P/E.C., the bank in pro-
gramming accepts only the RSR (Read Status
Register) instruction. See Figure 17 for Double
Word Program Flowchart and Pseudo code.
Tetra Word Program (TPG)
This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel. The first command must be given to the
target block and only one partition can be pro-
grammed at a time; the other partition must be in
one of the read modes or in the erase suspended
mode (see Table 8).
The four words must differ only for the addresses
A0 and A1. Programming should not be attempted
when VPP is not at VPPH. The operation can also
be executed if VPP is below VPPH but result could
be uncertain. These instruction uses five write cy-
cles. The first command written is the Tetra Word
Program Set-Up command 55h. A second write
operation latches the Address and the Data of the
first wordtobewritten, thethird writeoperation
latches the Address and the Data of the second
word to be written, the fourth write operation latch-
es the Address and the Data of the third word to be
written, the fifth write operation latches the Ad-
dress and the Data of the fourth word to be written
and starts the P/E.C. (see Table 11).
Read operations in the targeted bank output the
Status Register content after the programming
has started. The Status Register bit b7 returns '0'
while the programming is in progress and '1' when
it has completed. After completion the Status reg-
ister bit b4 returns '1' if there has been a Program
Failure. Status register bit b1 returns '1' if the user
is attempting to program a protected block. Status
Register bit b3 returns a '1' if VPP is below VPPLK.
Any attempt to write a ’1’ to an already pro-
grammed bit will result in a program fail (status
register bit b4 set). (See Table 12).
Programming aborts if RP goes to VIL.Asdata in-
tegrity cannot be guaranteed when the program
operation is aborted, the memory location must be
erased and reprogrammed. A Clear Status Regis-
ter instruction must be issued to reset b5, b4, b3
and b1 of the Status Register. During the execu-
tion of the program by the P/E.C., the bank in pro-
gramming accepts only the RSR (Read Status
Register) instruction. See Figure 17 for Tetra Word
Program Flowchart and Pseudo code.
Erase Suspend/Resume (PES/PER)
The Erase Suspend freezes, after a certain laten-
cy period (within 25us), the erase operation and al-
lows read in another block within the targeted bank
or program in the other block.
This instruction uses one write cycle B0h and the
address should be within the bank with the block
in erase (see Table 11). The device continues to
output status register data after the erase suspend
is issued. The status register bit b7 and bit b6 are
set to ’1’ then the erase operation has been sus-
pended. Bit b6 is set to '0' in case the erase is com-
pleted or in progress (see Table 12).
The valid commands while erase is suspended
are: Program/Erase Resume, Program, Read
Memory Array, Read Status Register, Read Elec-
tronic Signature, CFI Query, Block Protect, Block
Unprotect and Block Lock. The user can protect
the Block being erased issuing the Block Protect
or Block Lock commands.
During a block erase suspend, the device goes
into standby mode by taking E to VIH, which reduc-
es active current draw. Erase is aborted if RP turns
to VIL.
If an Erase Suspend instruction was previously ex-
ecuted, the erase operation may be resumed by
issuing the command D0h using an address within
the suspended bank. The status register bit b6 and
bit b7 are cleared when erase resumes and read
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