參數(shù)資料
型號: M58LW064A150T1T
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories
中文描述: 64兆位x16和x16/x32,塊擦除低壓閃存
文件頁數(shù): 32/53頁
文件大?。?/td> 319K
代理商: M58LW064A150T1T
M58LW064A, M58LW064B
32/53
Table 25. Synchronous Burst Read
(T
A
= 0 to 70
°
C, –40 to 85
°
C, V
DD
= 2.7V to 3.6V, V
DD
= 1.8V to V
DD
)
Note: 1. Data output should be read on the valid clock edge.
2. For paramters not listed see Asynchronous Read.
Symbol
(2)
Parameter
Test Condition
Min
Max
Unit
t
AVLL
Address Valid to Latch Enable Low
E = V
IL
10
ns
t
BHKH
Burst Address Advance High toValid Clock Edge
E = V
IL
, G = V
IL
, L = V
IH
10
ns
t
BLKH
Burst Address Advance Low to Valid Clock Edge
E = V
IL
, G = V
IL
, L = V
IH
10
ns
t
ELLL
Chip Enable Low toLatch Enable low
0
ns
t
GLKH
Output Enable Low to Valid Clock Edge
E = V
IL
, L = V
IH
20
ns
t
KHAX
Valid Clock Edge to Address Transition
E = V
IL
0
ns
t
KHLL
Valid Clock Edge to Latch Enable Low
E = V
IL
0
ns
t
KHLX
Valid Clock Edge to Latch Enable Transition
E = V
IL
0
ns
t
KHQX
Valid Clock Edge to Output Transition
E = V
IL
, G = V
IL
, L = V
IH
6
ns
t
LLKH
Latch Enable Low to Valid Clock Edge
E = V
IL
10
ns
t
QVKH(1)
Output Valid to Valid Clock Edge
E = V
IL
, G = V
IL
, L = V
IH
10
ns
t
RLKH
Valid Data Ready Low to Valid Clock Edge
E = V
IL
, G = V
IL
, L = V
IH
10
ns
Figure 12. Synchronous Burst Read (9.1.1.1 example)
X-Latency = 0 (M14-M11 = 0100), Y-Latency = 1 (M9 = 0), Burst Length = 4 (M2-M0 = 001),
Burst Type = Sequential (M7 = 1), Valid Clock Edge = Rising (M6 = 1)
AI03698
K
(1)
For set up signals and timings see Synchronous Burst Read 8.1.1.1
14
13
12
11
10
9
DQ0-DQx
tQVKH
tKHQX
Q0
Q1
Q2
Q3
Q0
Q1
SETUP
(1)
Burst
Read
Q0 to Q3
Burst Read Wraps if
Device
remains Selected (E = VIL)
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