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參數(shù)資料
| 型號： | M58LW064 |
| 廠商： | 意法半導體 |
| 英文描述： | 64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories |
| 中文描述： | 64兆位x16和x16/x32，塊擦除低壓閃存 |
| 文件頁數(shù)： | 11/53頁 |
| 文件大?。?/td> | 319K |
| 代理商： | M58LW064 |
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M58LW064A, M58LW064B
Burst Clock (K).
The Burst Clock K is used only
in burst mode. It is the fundamental synchronous
signal that allows internal latching of the address
from the address bus, together with Latch Enable
L; increment of the internal address counter in as-
sociation with Burst Address Advance B;and to in-
dicate valid data on the external data bus. All
these operations are synchronously controlled on
the valid edge of the Burst Clock K, which can be
selected to be the rising or falling edge depending
on the definition in the Burst Configuration Regis-
ter.
For Asynchronous Read or Write, the Burst Clock
K input level is Don’t Care. For Synchronous Burst
Read the address is latched on thefirst valid clock
edge when Latch Enable L is at V
IL
, or the rising
edge of Latch Enable L, whichever occurs first.
Burst Address Advance (B).
Burst Address Ad-
vance Benables increment of the internal address
counter when it falls to V
IL
during Synchronous
Burst Read. It is sampled on the last valid edge of
the Burst Clock K at the expiry of the X-latency
time. If sampled at V
IL
, new data will be output on
the next Burst Clock K valid edge (or second next
depending onthe definition in the Burst Configura-
tion Register). If it is at V
IH
when sampled, thepre-
vious data remains on theDataOutputs. The Burst
Address Advance B may be tied to V
IL
.
Ready (R).
The Valid Data Ready R is an output
signal used during Synchronous Burst Read. It in-
dicates, at the valid clock edge (or one cycle be-
fore depending on the definition in the Burst
Configuration Register), if valid data is ready on
the Data Outputs. New Data Outputs are valid if
Valid Data Ready R is at V
IH
, the previous Data
Outputs remain active if Valid Data Ready R is at
V
IL
.
In all operations except Burst Read, Valid Data
Ready R is at V
IH
. It may be tied to other compo-
nents with the same Valid Data Ready R signal to
create a unique system Ready signal. The Valid
Data Ready R output has an internal pull-up resis-
tor ofaround 1 M
poweredfrom V
DDQ
, designers
should use an external pull-up resistor of the cor-
rect value to meet the external timing require-
ments for R going to V
IH
.
Word Organisation (WORD).
The Word Organi-
sation WORD input is present only on the
M58LW064B and selects x16 or x32 organisation.
The WORD input selects the data width as Word
wide (x16) or Double-Word wide (x32). When
WORD is at V
IL
, Word-wide x16 width is selected
and data is read and programmedon DQ0-DQ15,
DQ16-DQ31 are at high impedance and A1 is the
LSB address. When WORD is at V
IH
, the Double-
Word wide x32 width is selected and the data is
read and programmed on DQ0-DQ31, and A2 is
the LSB address.
Ready/Busy (RB).
Ready/Busy RB is an open-
drain output and gives the internal state of the P/
E.C. When Ready/Busy RB is at V
IL
the device is
busy with a Program or Erase operation and it will
not accept any additional program or erase in-
structions except for the Program or Erase Sus-
pend instructions. When a Program or Erase
Suspend is given the RB signal rises to V
IH
, after
a latency time, to indicatethat theCommand Inter-
face is ready for a new instruction. When RB is at
V
IH
, the device is ready for any Read, Program or
Erase operation. Ready/Busy RB is also at V
IH
when the memory isin Erase/Program Suspendor
Standby modes.
Program/Erase Enable (V
PP
).
Program/Erase
Enable V
PP
automatically protects all blocks from
programming or erasure when at V
IL
.
Supply Voltage (V
DD
).
The Supply Voltage V
DD
is the main power supply for all operations (Read,
Program and Erase).
Input/Output Supply Voltage (V
DDQ
).
The
put/Output Supply Voltage V
DDQ
is the Input and
Output buffer power supply for all operations
(Read, Program and Erase).
Ground (V
SS
).
Ground V
SS
isthe reference for all
the voltage measurements.
In-
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| M58LW064A150ZA6T | 64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M58LW064A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories |
| M58LW064A150N1 | 功能描述:閃存 8Mx8 or 4Mx16 150ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M58LW064A150NF1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories |
| M58LW064A150NF6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories |
| M58LW064A150NH1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories |
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