參數(shù)資料
型號: M58LW032CN
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
中文描述: 32兆位的2Mb x16插槽,統(tǒng)一座,突發(fā)3V電源快閃記憶體
文件頁數(shù): 40/61頁
文件大小: 845K
代理商: M58LW032CN
M58LW032C
40/61
Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output
Note: 1. Valid Data Ready = Valid Low during valid clock edge (CR8 = 0)
2. V= Valid output, NV= Not Valid output.
3. R is an open drain output with an internal pull up resistor of 1M
.
Depending on the Valid Data Ready pin capacitance load an
external pull up resistor must be chosen according to the system clock period.
Table 20. Synchronous Burst Read AC Characteristics
Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
Symbol
Parameter
M58LW032C
Unit
90, 110
t
AVKH
Address Valid to Active Clock Edge
Min
7
ns
t
AVLH
Address Valid to Latch Enable High
Min
10
ns
t
ELKH
Chip Enable Low to Active Clock Edge
Min
10
ns
t
ELLH
Chip Enable Low to Latch Enable High
Min
10
ns
t
GLKH
Output Enable Low to Valid Clock Edge
Min
20
ns
t
KHAX
Valid Clock Edge to Address Transition
Min
5
ns
t
KHLL
Valid Clock Edge to Latch Enable Low
Min
0
ns
t
KHLH
Valid Clock Edge to Latch Enable High
Min
0
ns
t
KHQX
Valid Clock Edge to Output Transition
Min
3
ns
t
LLKH
Latch Enable Low to Valid Clock Edge
Min
6
ns
t
LLLH
Latch Enable Low to Latch Enable High
Min
7
ns
t
KHQV
Valid Clock Edge to Output Valid
Max
15
ns
t
QVKH
Output Valid to Active Clock Edge
Min
5
ns
t
RLKH
Valid Data Ready Low to Valid Clock Edge
Min
5
ns
AI05510
K
Output
(2)
V
V
NV
NV
V
V
tRLKH
R
V
(3)
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