參數(shù)資料
型號: M58LR128FB95ZB6E
廠商: NUMONYX
元件分類: PROM
英文描述: 8M X 16 FLASH 1.8V PROM, 95 ns, PBGA56
封裝: 7.70 X 9 MM, 0.75 MM PITCH, LEAD FREE, VFBGA-56
文件頁數(shù): 64/82頁
文件大小: 1303K
代理商: M58LR128FB95ZB6E
67/82
M58LR128FT, M58LR128FB
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, There are two Bank Regions, see Table 29. and Table 30.
(P+3C)h = 146h
64h
(P+44)h = 14Eh
64h
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
(P+3D)h = 147h
00h
(P+45)h = 14Fh
00h
(P+3E)h = 148h
02h
(P+46)h = 150h
02h
Bank Region 2 (Erase Block Type 1): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+3F)h = 149h
03h
(P+47)h = 151h
03h
Bank Region 2 (Erase Block Type 1):Page mode and
Synchronous mode capabilities (defined in Table 37.)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+40)h = 14Ah
03h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+44)h =14Eh
64h
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+45)h = 14Fh
00h
(P+46)h = 150h
02h
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+47)h = 151h
03h
Bank Region 2 (Erase Block Type 2): Page mode and
Synchronous mode capabilities (defined in Table 37.)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h
Feature Space definitions
(P+49)h = 153h
(P+43)h = 153h
Reserved
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
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