參數(shù)資料
型號： M58BW016DB90ZA6FT
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 512K X 32 FLASH 3V PROM, 90 ns, PBGA80
封裝： 10 X 12 MM, 1 MM PITCH, LBGA-80
文件頁數(shù)： 16/63頁
文件大?。?/td> 901K
代理商： M58BW016DB90ZA6FT
23/63
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
9, Commands. Refer to Table 9 in conjunction with
the text descriptions below.
Read Memory Array Command
The Read Memory Array command returns the
memory to Read mode. One Bus Write cycle is re-
quired to issue the Read Memory Array command
and return the memory to Read mode. Subse-
quent read operations will output the addressed
memory array data. Once the command is issued
the memory remains in Read mode until another
command is issued. From Read mode Bus Read
commands will access the memory array.
Read Electronic Signature Command
The Read Electronic Signature command is used
to read the Manufacturer Code, the Device Code
or the Burst Configuration Register. One Bus Write
cycle is required to issue the Read Electronic Sig-
nature command. Once the command is issued
subsequent Bus Read operations, depending on
the address specified, read the Manufacturer
Code, the Device Code or the Burst Configuration
Register until another command is issued; see Ta-
ble 5, Read Electronic Signature.
Read Query Command.
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area. One Bus Write cycle is required to issue the
Read Query Command. Once the command is is-
sued subsequent Bus Read operations, depend-
ing on the address specified, read from the
Common Flash Interface Memory Area. See Ap-
pendix A, Tables 25, 26, 27, 28 and 29 for details
on the information contained in the Common Flash
Interface (CFI) memory area.
Read Status Register Command
The Read Status Register command is used to
read the Status Register. One Bus Write cycle is
required to issue the Read Status Register com-
mand. Once the command is issued subsequent
Bus Read operations read the Status Register un-
til another command is issued.
The Status Register information is present on the
output data bus (DQ1-DQ7) when Chip Enable E
and Output Enable G are at VIL and Output Dis-
able is at VIH.
An interactive update of the Status Register bits is
possible by toggling Output Enable or Output Dis-
able. It is also possible during a Program or Erase
operation, by disactivating the device with Chip
Enable at VIH and then reactivating it with Chip En-
able and Output Enable at VIL and Output Disable
at VIH.
The content of the Status Register may also be
read at the completion of a Program, Erase or
Suspend operation. During a Block Erase, Pro-
gram, Tuning Protection Program or Tuning Pro-
tection Unlock command, DQ7 indicates the
Program/Erase Controller status. It is valid until
the operation is completed or suspended.
See the section on the Status Register and Table
11 for details on the definitions of the Status Reg-
ister bits
Clear Status Register Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One Bus Write is required to issue the Clear
Status Register command. Once the command is
issued the memory returns to its previous mode,
subsequent Bus Read operations continue to out-
put the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Pro-
gram, Erase, Block Protect or Block Unprotect
command is issued. If any error occurs then it is
essential to clear any error bits in the Status Reg-
ister by issuing the Clear Status Register com-
mand before attempting a new Program, Erase or
Resume command.
Block Erase Command
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ‘1’. All
previous data in the block is lost. If the block is pro-
tected then the Erase operation will abort, the data
in the block will not be changed and the Status
Register will output the error.
Two Bus Write operations are required to issue the
command; the first write cycle sets up the Block
Erase command, the second write cycle confirms
the Block erase command and latches the block
address in the internal state machine and starts
the Program/Erase Controller. The sequence is
aborted if the Confirm command is not given and
the device will output the Status Register Data with
bits 4 and 5 set to '1'.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. During the
Erase operation the memory will only accept the
Read Status Register command and the Program/
Erase Suspend command. All other commands
will be ignored.
The command can be executed using either VDD
(for a normal erase operation) or VPP (for a fast
erase operation). If VPP is in the VPPH range when
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