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參數(shù)資料
| 型號： | M54HCT533 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Octal D Type Latch(八D鎖存器(三態(tài)輸出)) |
| 中文描述： | 八路D型鎖存器（八?鎖存器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 269K |
| 代理商： | M54HCT533 |
M54/74HCT373
M54/74HCT533
October 1993
HCT373 NON INVERTING - HCT533 INVERTING
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OL
=
I
OH
= 6 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS373/533
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
B1R
(Plastic Package)
ORDER CODES :
M54HCTXXXF1R
M74HCTXXXB1R
M74HCTXXXM1R
M74HCTXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTION
(top view)
HCT373
.
HIGH SPEED
t
PD
= 17 ns(TYP.) AT V
CC
= 5 V
DESCRIPTION
The M54/74HCT373 and M54HCT533 are high
speed CMOS OCTAL LATCH WITH 3-STATE
OUTPUTS fabricated with in silicon gate C
2
MOS
technology.
These ICs achive the high speed operation similar
to equivalent LSTTL while maintaning the CMOS
low power dissipation.
These 8 bit D-Type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
willbelatchedprecisely orinversely atthelogiclevel
of D input data. While the OE input is at low level,
the eight outputs will be in a normal logic state (high
or low logiclevel) and while high level theoutpts will
be in a high impedance state. The application
designer has a choise of combination of inverting
and non inverting outputs. The three state output
configuration and the wide choise of outline make
bus organized system simple.
These integrated circuits have input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are
designed to directly interface HSC
2
MOS systems
with TTL and NMOS components. They are also
plug in replacements for LSTTL devices giving a
reduction of power consumption. All inputs are
equipped with protection circuits against discharge
and transient excess voltage.
HCT533
HCT373
HCT533
1/13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M54HCT373 | Octal D Type Latch(八D鎖存器(三態(tài)輸出)) |
| M54HCT534 | Octal D Type Trigger(八D觸發(fā)器(三態(tài)輸出)) |
| M54HCT374 | Octal D Type Trigger(八D觸發(fā)器(三態(tài)輸出)) |
| M54HCT540 | Octal Bus Buffer With 3-State Output(八總線緩沖器(三態(tài)輸出)) |
| M54HCT563 | Octal D Type Latch With 3-State Output(八D鎖存器(三態(tài)輸出)) |
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