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參數(shù)資料
| 型號(hào)： | M54HCT165 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Bit PISO Shift Register(8位并入串出移位寄存器) |
| 中文描述： | 8位皮索移位寄存器（8位并入串出移位寄存器） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 277K |
| 代理商： | M54HCT165 |
M54HCT165
M74HCT165
October 1993
8 BIT PISO SHIFT REGISTER
B1R
(Plastic Package)
ORDER CODES :
M54HCT165F1R
M74HCT165B1R
M74HCT165M1R
M74HCT165C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
.
HIGH SPEED
t
PD
= 17 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OL
=
I
OH
= 4 mA(MIN.)
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2 V (MIN.) V
IL
= 0.8V (MAX.)
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS165
DESCRIPTION
The M54/74HCT165 is a high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated in silicon gate
C
2
MOS technology. It has the same high speed
performance of LSTTL combined with true CMOS
low power consumption. It achives the high speed
operation
similar
to
equivalent
maintaining the CMOS low power dissipation.
Thisdevice contains eight clocked master slave RS
flip-flops connected as a shift register, with auxiliary
gating to provide over-riding asynchronous parallel
entry.Parallel data entrenswhentheshift/loadinput
is low. The parallel data can change while shift/load
is low, provided that the recommended set-up and
hold times are observed. For clocked operation,
shift/load mustbe high. The twoclock inputperform
identically; one can be used as a clock inhibit by
applying a high signal; to permit this operation
clocking is accomplished through a 2 input nor
gates.
To avoiddoubleclocking,however, the inhibit signal
should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the
same response as risingclock edge.This integrated
circuit has input and output characteristics that are
fully compatible with 54/74 LSTTL logic families.
M54/74HCT devices are designed to directly
interface HSCMOS systems with TTL and NMOS
components. They are alsoplug in replacements for
LSTTL devices giving a reduction of power
consumption.
All
inputs
protection circuits against static discharge and
transient excess voltage.
LSTTL while
are
equipped
with
1/13
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