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參數(shù)資料
| 型號： | M54HCT138 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3 TO 8 LINE DECODER INVERTING |
| 中文描述： | 3至8線譯碼器反相 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 242K |
| 代理商： | M54HCT138 |
M54HCT138
M74HCT138
February 1993
3 TO 8 LINE DECODER (INVERTING)
B1R
(Plastic Package)
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
ORDER CODES :
M54HCT138F1R
M74HCT138B1R
M74HCT138M1R
M74HCT138C1R
DESCRIPTION
The M54/74HC138 is a highspeed CMOS 3 TO 8
LINE DECODER fabricated in silicon gate C
2
MOS
technology. It has the same high speed perform-
anceofLSTTL combinedwithtrue CMOSlowpower
consumption. If the device is enabled, 3 binaryse-
lect inputs (A, Band C) determine whichone of the
outputs will go low.If enable input G1 is held lowor
eitherG2A or G2B is held high, the decoding func-
tion is inhibited and all the8 outputs go high. Three
enableinputsare provided toease cascadeconnec-
tion and application of address decoders for mem-
ory systems.All inputs are equipped with protection
circuits against static discharge and tran- sient ex-
cess voltage.This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC
2
MOS sys-
tems with TTL and NMOS components. They are
also plugin replacements for LSTTL devices giving
a reduction of power consumption.
.
HIGH SPEED
t
PD
= 16 ns(TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
AAT T
A
= 25
°
C
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS138
1/10
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