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參數(shù)資料
| 型號： | M54HC77F1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4-BIT D-TYPE LATCH |
| 中文描述： | 4位D型鎖存 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 241K |
| 代理商： | M54HC77F1R |
M54HC77
M74HC77
October 1992
4-BIT D-TYPE LATCH
B1R
(Plastic Package)
ORDER CODES :
M54HC77F1R
M74HC77B1R
M74HC77M1R
M74HC77C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
t
PD
= 10 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 2
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS77
The M54/74HC77 is a high speed CMOS 4-BIT D-
TYPELATCH fabricated in silicon gate C
2
MOStech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. It contains two groups of2-bit latches con-
trolled by an enable input (G1
2 or G3
4). These
twolatch groups canbe usedin different circuits.The
dataapplied tothedata inputs (1D,2D,or3D,4D)are
transfered to the Q outputs (1Q, 2Q, or 3Q, 4Q) re-
spectively when the enable input (G1
2or G3
4) is
taken high. The Q outputs will follow the data inputs
aslong asthe enable input iskepthigh.Whenthe en-
ableinput istaken low,theinformation data applied to
thedata inputs is retained at the Q outputs. All inputs
areequipped withprotection circuitsagainststaticdis-
charge and transient excess voltage.
DESCRIPTION
1/10
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