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參數(shù)資料
| 型號： | M54HC74K1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14 |
| 封裝： | CERAMIC, DFP-14 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 281K |
| 代理商： | M54HC74K1 |
1/12
June 2004
s
HIGH SPEED:
fMAX = 67MHz (TYP.) at VCC =6V
s
LOW POWER DISSIPATION:
ICC =2A(MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH =VNIL = 28% VCC (MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 74
s
SPACE GRADE-1: ESA SCC QUALIFIED
s
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s
DEVICE FULLY COMPLIANT WITH
SCC-9203-050
DESCRIPTION
The M54HC74 is an high speed CMOS DUAL D
TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C2MOS technology.
A signal on the D INPUT is transferred on the Q
OUTPUT during the positive going transition of the
clock
pulse.
CLEAR
and
PRESET
are
independent of the clock and accomplished by a
low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC74
RAD HARD DUAL D TYPE FLIP FLOP
WITH PRESET AND CLEAR
PIN CONNECTION
ORDER CODES
PACKAGE
FM
EM
DILC
M54HC74D
M54HC74D1
FPC
M54HC74K
M54HC74K1
Rev. 1
DILC-14
FPC-14
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