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參數(shù)資料
| 型號： | M54HC595 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Single Nanopower Push-Pull Comparator 8-SOIC -40 to 125 |
| 中文描述： | 8位元移位寄存器與輸出鎖存器三態(tài) |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 282K |
| 代理商： | M54HC595 |
M54HC595
M74HC595
April1993
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)
.
HIGH SPEED
f
MAX
= 55 MHz (TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS FOR QA TO QH
10 LSTTL LOADS FOR QH’
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN.) FOR QA TOQH
|I
OH
| = I
OL
= 4 mA (MIN.) FOR QH’
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH LSTTL 54/74LS595
B1R
(Plastic Package)
ORDER CODES :
M54HC595F1R
M74HC595B1R
M74HC595M1R
M74HC595C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
The M54/74HC595 is a high speed CMOS 8-BIT
SHIFT
REGISTERS/OUTPUT
STATE) fabricated in silicon C
2
MOS technology. It
has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage reg-
ister. The storageregister has 8 3-STATE outputs.
Separate clocks are provided for both the shift reg-
isterand the storage register.
The shift register has adirect-overriding clear, serial
input, and serial output (standard) pins for cascad-
ing. Both the shift register and storage register use
positive-edge triggered clocks. If both clocks are
connected together, the shift register state will al-
ways be one clock pulse ahead of the storagereg-
ister.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
LATCHES
(3-
1/13
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