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參數(shù)資料
| 型號： | M54HC4094F1R |
| 廠商： | 意法半導體 |
| 英文描述： | 8 BIT SIPO SHIFT LATCH REGISTER 3-STATE |
| 中文描述： | 8位國家知識產(chǎn)權(quán)局位移鎖存寄存器三態(tài) |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 270K |
| 代理商： | M54HC4094F1R |
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
-40 to 85
o
C
74HC
Min.
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
Min.
Typ.
30
-55 to 125
o
C
54HC
Min.
Max.
75
15
13
200
40
34
150
30
26
160
32
27
150
30
26
150
30
26
Max.
95
19
16
250
50
43
190
38
32
200
40
34
190
38
32
190
38
32
Max.
110
22
19
300
60
51
225
45
38
240
48
41
225
45
38
225
45
38
t
TLH
t
THL
Output Transition
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
ns
8
7
t
PLH
t
PHL
Propagation
Delay Time
(CLOCK - Qn)
92
26
20
65
19
15
75
20
16
58
16
13
35
16
13
16
66
80
17
7
6
28
6
6
30
7
5
45
10
8
ns
t
PLH
t
PHL
Propagation
Delay Time
(CLOCK-QS,Q’S)
ns
t
PLH
t
PHL
Propagation
Delay Time
(STROBE - Qn)
ns
t
PZL
t
PZH
3 State Output
Enable Time
ns
t
PHZ
t
PLZ
3 State Output
Disable Time
ns
f
MAX
Maximum Clock
Frequency
6
30
35
4.8
24
28
4
MHz
20
24
t
W(H)
t
W(L)
Minimum Pulse
Width
75
15
13
75
15
13
75
15
13
100
20
17
0
0
0
10
95
19
16
95
19
16
95
19
16
125
25
21
0
0
0
10
110
22
19
110
22
19
110
22
19
145
29
25
0
0
0
10
ns
t
W(L)
Minimum Pulse
Width
ns
t
s
Minimum Set-up
Time
(SI)
ns
t
s
Minimum Set-up
Time
(ST)
ns
t
h
Minimum Hold
Time
(SI, ST)
ns
C
IN
Input Capacitance
Power Dissipation
Capacitance
5
pF
C
PD
(*)
140
pF
(*) C
PD
isdefined asthe value ofthe IC’sinternal equivalent capactance which is calculated from the operating current consumption without load.
(Refer to Test Circuit).Average operting current can be obtained by thefollowingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/2(per FLIP/FLOP)
M54/M74HC4094
6/12
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