參數(shù)資料
型號(hào): M54HC292C1R
廠商: 意法半導(dǎo)體
英文描述: Low-Power Stereo DAC with HP Amplifier 28-TSSOP -10 to 70
中文描述: 可編程分頻器/定時(shí)器
文件頁數(shù): 1/14頁
文件大?。?/td> 299K
代理商: M54HC292C1R
M54/74HC292/7292
M54/74HC294/7294
October 1993
PROGRAMMABLE DIVIDER/TIMER
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTION
(top view)
.
HIGH SPEED
f
MAX
= 70 MHz (TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4 mA (MAX.) at T
A
= 25
o
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
| I
OH
|= I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS292/294
DESCRIPTION
The 54/74HC292/7292 and HC294/7294 are high
speedCMOSPROGRAMMABLEDIVIDER/TIMER
fabricated with silicon C
2
MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
These
devices are
programmable
dividers. Thetypeshavetwoclockinputs,eitherone
may be used for clock gating. (see the function
table). The HC292/7292 can divide from 2
2
to 2
31
,
and the HC294/7294 can divide from2
2
to2
15
. The
frequency
types feature an active-low clear input to initialize
the state of all flip-flops. To facilitate incoming
inspection, test points are provided. (TP1, TP2 and
TP3
on
the
HC292/7292
HC294/7294).
All
inputs
protection circuits against static discharge and
transient excess voltage.
HC292/294 have Q output with ”Totem pole”
configuration and test point TP with ”O(jiān)pen Drain”
output configuration.
HC7292/7294 have all outputs ”Totem Pole”.
and
TP
on
the
with
are
equipped
HC292
HC7292
HC294
HC7294
HC292
HC7292
HC294
HC7294
1/14
相關(guān)PDF資料
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