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參數(shù)資料
| 型號(hào)： | M54HC280K |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 算術(shù)邏輯單元 |
| 英文描述： | HC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14 |
| 封裝： | CERAMIC, DFP-14 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 193K |
| 代理商： | M54HC280K |
1/9
April 2004
s
HIGH SPEED:
tPD = 22ns (TYP.) at VCC =6V
s
LOW POWER DISSIPATION:
ICC =4A(MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH =VNIL = 28% VCC (MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 280
s
SPACE GRADE-1: ESA SCC QUALIFIED
s
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s
DEVICE FULLY COMPLIANT WITH
SCC-9208-003
DESCRIPTION
The M54HC280 is an high speed CMOS 9-BIT
PARITY GENERATOR fabricated with silicon gate
C2MOS technology.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (
ΣODD and ΣEVEN). The nine
data inputs control the output conditions. When
the number of high level input is odd,
ΣODD
output is kept high and
ΣEVEN output low.
Conversely, when the output is even,
ΣEVEN
output is kept high and
ΣODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC280
RAD-HARD 9 BIT PARITY GENERATOR
PIN CONNECTION
ORDER CODES
PACKAGE
FM
EM
DILC
M54HC280D
M54HC280D1
FPC
M54HC280K
M54HC280K1
DILC-14
FPC-14
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